Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-05-09
2003-06-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S768000, C438S244000, C438S386000, C148SDIG001
Reexamination Certificate
active
06583021
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the invention relates to a method for fabricating a capacitor thereof.
2. Brief Description of Related Technology
As an integration of a semiconductor device becomes higher recently, studies are conducted to increase the charge storage area by forming a capacitor in a complicated structure such as a cylinder, fin, stack or hemispheric silicon (HSG) to secure sufficient capacitance. In addition, a dielectric layer of capacitor is formed of materials HfO
2
, Al
2
O
3
, Ta
2
O
5
, SrTiO
3
, (Ba,Sr)TiO
3
, BLT, etc., of which dielectric constants are higher than SiO
2
or Si
3
N
4
. In particular, a hafnium oxide (HfO
2
) layer is a high dielectric layer currently studied for a gate insulation layer and a dielectric layer of a capacitor.
FIGS. 1A
to
1
C are cross-sectional views illustrating a conventional method for fabricating a capacitor.
Referring to
FIG. 1A
, an inter-layer dielectric layer (ILD)
12
is formed on a surface of a semiconductor substrate
11
having transistors and bit lines, and a storage node contact mask (not shown) is formed on inter-layer dielectric layer (ILD)
12
. After that, a storage node contact hole is formed to expose a predetermined area of the surface of the semiconductor substrate
11
by etching the inter-layer dielectric layer
12
with the storage node contact mask.
Subsequently, a polysilicon layer is formed on the entire surface including the storage node contact hole, and then an etch-back process is carried out in order to form a polysilicon plug
13
in the contact hole to a predetermined depth.
After that, a titanium silicide (TiSi
2
)
14
and a titanium nitride (TiN) layer
15
are formed on the polysilicon plug
13
. The TiSi
2
layer
14
forms an ohmic contact with a following bottom electrode, and the TiN layer
15
serves as an anti-diffusion layer that prevents oxygen remaining inside the bottom electrode from diffusing into the polysilicon plug
13
, the storage node contact plug, or into the semiconductor substrate
11
.
Referring to
FIG. 1B
, a sacrificial oxide layer
16
that determines the height of the bottom electrode is formed on the inter-layer dielectric layer
12
and the TiN layer
15
, and then a storage node mask (not shown) using a photoresist is formed on the sacrificial oxide layer
16
.
Subsequently, the sacrificial oxide layer
16
is selectively etched with the storage node mask to form an opening in which a bottom electrode is aligned on the polysilicon plug
13
to be formed.
Thereafter, a bottom electrode
17
is formed of metal over the surface of the sacrificial oxide layer
16
including the opening. After that, the bottom electrode is made to remain in the opening only through the process of etch-back or chemical mechanical polishing method so that the bottom electrode in the concavity is isolated from the neighboring bottom electrodes.
Referring to
FIG. 1C
, on the entire surface including the bottom electrode
17
, a dielectric layer
18
and a top electrode
19
are formed successively. Here, the bottom electrode
17
, dielectric layer
18
and top electrode
19
are formed by the chemical vapor deposition (CVD) method, and the dielectric layer
18
is mostly made of a high dielectric layer, such as HfO
2
.
In the conventional method described above, a capacitor is formed connected to a plug by using a storage node contact mask.
However, in a dynamic RAM (DRAM) over 4 Gbits that a fine design rule should be applied to, the storage node contact plug and the bottom electrode should not be misaligned. Also, to secure a sufficient capacitance, the height of the bottom electrode should be increased. This is a difficult because the plug height for interconnection becomes higher as the height of the bottom electrode gets higher. In addition, because the isolation gap from the neighboring bottom electrode is reduced, the current technology forming a bottom electrode, dielectric layer and top electrode by the CVD method has reached its limitation, so an atomic layer deposition (ALD) method is under development recently.
However, the ALD method has a shortcoming that an extra thermal treatment, or plasma treatment should be performed in every step to improve the quality of the layers. This is because the ALD method conducts depositions at a low temperature to improve the step coverage. Due to such complicated processes and investment for new equipments, the production costs are high for the ALD method.
It would be desirable to provide a method for fabricating a capacitor that avoids a rise in the production cost and complexity in production processes caused by performing a deposition and a subsequent treatment thereof whenever a layer is formed.
It also would be desirable to provide a method for fabricating a capacitor that avoids a misalignment in masking or etching processes for connecting transistors and the capacitor.
SUMMARY OF THE INVENTION
Accordingly, disclosed herein is a method of fabricating a capacitor, comprising the steps of: (a) forming a Ti
1−x
Hf
x
N layer on a substrate, wherein x is in a range from 0 to 0.5; (b) forming an electrode layer on the Ti
1−x
Hf
x
N layer; and, (c) forming a HfO
2
layer on an interface between the electrode layer and the Ti
1−x
Hf
x
N layer by performing a thermal treatment in an oxygen gas-containing atmosphere. Such a capacitor will include a bottom electrode formed from the Ti
1−x
Hf
x
N layer, a dielectric layer formed from the HfO
2
layer, and a top electrode formed from the electrode layer.
Also disclosed herein is a method for fabricating a capacitor, comprising the steps of: (a) forming an inter-layer dielectric layer on a silicon semiconductor substrate; (b) forming a contact hole that exposes a surface of the semiconductor substrate by selectively etching the inter-layer dielectric layer; (c) forming a Ti
1−x
Hf
x
N layer in the contact hole, wherein x is in a range from 0 to about 0.5; (d) forming an electrode layer on the Ti
1−x
Hf
x
N layer; and forming a HfO
2
layer on an interface between the electrode layer and the Ti
1−x
Hf
x
N layer by performing a thermal treatment in an oxygen atmosphere. Such a capacitor will include a bottom electrode formed from the Ti
1−x
Hf
x
N layer, a dielectric layer formed from the HfO
2
layer, and a top electrode formed from the electrode layer.
REFERENCES:
patent: 4432035 (1984-02-01), Hsieh et al.
patent: 4839011 (1989-06-01), Ramalingam et al.
patent: 4920071 (1990-04-01), Thomas
patent: 4931896 (1990-06-01), LeCourt
patent: 5292609 (1994-03-01), Yoshikawa et al.
patent: 5414301 (1995-05-01), Thomas
patent: 5610853 (1997-03-01), Akiyama et al.
patent: 5641702 (1997-06-01), Imai et al.
patent: 5741722 (1998-04-01), Lee
patent: 6436723 (2002-08-01), Tomita et al.
patent: 2001/0000923 (2001-05-01), Takemura
patent: 2001/0016382 (2001-08-01), Song et al.
patent: 2002/0028556 (2002-03-01), Marsh et al.
patent: 2003/0036242 (2003-02-01), Yang
patent: 60-107588 (1986-11-01), None
patent: 63-047945 (1989-09-01), None
Fourson George
García Joannie Adelle
Hynix / Semiconductor Inc.
Marshall Gerstein & Borun
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