Method of fabricating bipolar transistor having high speed and M

Details Method of fabricating bipolar transistor having high speed and M Method of fabricating bipolar transistor having high speed and M

1994-07-22

1996-04-09

Fourson, George

Fishing, trapping, and vermin destroying

437 59, 437 74, 437 75, 437153, 148DIG9, 257370, 257378, H01L 21265

Patent

active

055061567

ABSTRACT:
A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

REFERENCES:
patent: 4950616 (1990-08-01), Kahng et al.
patent: 5268309 (1993-12-01), Mizutani et al.
patent: 5340751 (1994-08-01), Maeda et al.

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