Method of fabricating bipolar semiconductor integrated circuit d

Details Method of fabricating bipolar semiconductor integrated circuit d Method of fabricating bipolar semiconductor integrated circuit d

1986-09-30

1988-03-15

Roy, Upendra

Fishing, trapping, and vermin destroying

437 33, 437 69, 437147, 437160, 437909, 437DIG1, 357 34, H01L 21265, H01L 21385

Patent

active

047313412

ABSTRACT:
An improved bipolar semiconductor integrated circuit device which has a reduced base resistance and a reduced parasitic capacitance can be provided with a small number of manufacturing steps.
A two-layered film composed of both a thin oxide film and a nitride film is formed on the surface of an impurity doped layer of a first conductivity type which is formed on a semiconductor substrate. A resist layer having an overhanging cross section is formed on a selected surface of the two-layered film. A high melting metal is deposited on the surface of the structure obtained by the above step in such manner that the metal does not cover the surface of the nitride film under the overhanging portion of the resist layer. The two-layered film under the overhanging portion of the resist layer is selectively removed to expose the surface of the impurity doped layer. A semiconductor material is deposited on an entire surface of the structure obtained by the above step, the semiconductor material being deposited under the overhanging portion of the resist layer. The resist layer is exposed to expose the surface of the nitride film.
Impurities of a second conductivity type are then implanted into the semiconducting material, the surface of the semiconductor oxidized, and impurities are diffused from the semiconductor material later to form a diffused region in said impurity doped layer. The exposed nitride and oxide films are then removed and a semiconductor material layer containing said first conductivity type impurities is formed on the exposed surface of the impurity doped layer.

REFERENCES:
patent: 4337115 (1982-06-01), Ikeda et al.
patent: 4417385 (1983-11-01), Temple
patent: 4481706 (1984-11-01), Roche
patent: 4545114 (1985-10-01), Ito et al.
patent: 4590666 (1986-05-01), Goto
patent: 4614416 (1987-02-01), Iranmanesh et al.
patent: 4640721 (1987-02-01), Uehara et al.
"High Speed Bipolar ICs Using Super Self-Aligned Process Technology", by Tetsushi Sakai et al., Japanese Journal of Applied Physics, vol. 20, (1981), Supplement 20-1, pp. 155-159.
"Deep UV Resist, LMR, for Lift-Off Technique", by Takaharu Kozu et al., The Electronic Communication Academic Institute Bulletin, SSD 83-178, pp. 1 to 8.

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