Method of fabricating BICMOS field effect transistors

Details Method of fabricating BICMOS field effect transistors Method of fabricating BICMOS field effect transistors

1991-09-20

1993-03-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 59, 148DIG9, 257526, H01L 2170, H01L 2700

Patent

active

051943964

ABSTRACT:
There is disclosed a method of fabricating BiCMOS semiconductor devices. External metal lines are not used for connecting the NPN bipolar device and NMOS device, or NPN bipolar device and PMOS device. In this case, the collector and base of the bipolar device are respectively in common with the drain and source of the CMOS. The bipolar transistor is in common with the bulk region of the CMOS, so that the diffusion layer is commonly used in the NPN-PMOS pair, and the diffusion layers of the connecting part are connected together in the NPN-PMOS pair. A metal line is connected to the junction of the diffusion layers, thus decreasing the connecting area of the metal line. Hence, the integrability of the chip is increased, and the metal connection causes a reduction of the RC delay time, thus improving the operational speed.

REFERENCES:
patent: 4868135 (1989-09-01), Ogura et al.

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