Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2001-05-09
2004-04-20
Booth, Richard A. (Department: 2812)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S140000, C349S142000, C438S030000
Reexamination Certificate
active
06724453
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2000-24965, filed on May 10, 2000, under 35 U.S.C. § 119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for use in an in-plane switching mode liquid crystal display device (IPS-LCD).
2. Description of Related Art
In general, liquid crystal display device (LCD) includes a display panel which have upper and lower substrates attached to each other with a liquid crystal layer interposed between the upper and lower substrates. These upper and lower substrates are respectively referred to as color filter and array substrates. Further, the display panel includes retardation films and polarizers on its exterior surfaces. Because the LCD device is selectively comprised of the above-mentioned elements, it converts the state of incident light and changes light refractive index in order to have great brightness and high contrast ratio.
Although the liquid crystal molecules in the liquid crystal layer are usually twisted nematic liquid crystals, use of the twisted nematic liquid crystal layer in the large-sized display panel is limited because of unstable transmittance of the twisted nematic liquid crystal layer, which depends on viewing angle. Moreover, the light transmittance varies depending on vertical viewing angle and is asymmetrically distributed compared to symmetric distribution in horizontal viewing angle. Thus, a range of reverse-image occurs when the viewing angle is vertically slanted. Thus, the viewing angle becomes narrow.
In order to solve the problem of the narrow viewing angle, in-plane switching liquid crystal display (IPS-LCD) devices have been proposed. IPS-LCD devices typically include a lower substrate where a pixel electrode and a common electrode are disposed, an upper substrate having no electrode, and a liquid crystal interposed between the upper and lower substrates. In this typical structure, the liquid crystal molecules are driven by a horizontal electric field. Contrast ratio is increased and color-shift is prevented. Thus, the characteristics of viewing angle are improved.
FIG. 1
is a plan view illustrating one pixel of an array substrate of a conventional in-plane switching mode liquid crystal display (IPS-LCD) device. As shown, a plurality of gate lines
14
are transversely disposed on a substrate (see reference element
11
of FIG.
2
A). A common line
12
is spaced apart from and disposed parallel with the gate lines
14
. A plurality of data lines
13
that are spaced apart from each other are disposed across and perpendicular to the gate and the common lines
14
and
12
. Each pair of gate and data lines
14
and
13
defines a pixel area “P”.
Near the crossing of the gate and data lines
14
and
13
, a switching device, i.e., a thin film transistor that is indicated by a portion “T”, is positioned. As shown in an enlarged view of a portion “T”, gate and source electrodes
21
and
17
are positioned and electrically connected with the gate and data lines
14
and
13
, respectively. A drain electrode
19
is spaced apart from the source electrode
17
and overlaps one end of the gate electrode
21
. The source electrode
17
also overlaps the other end of the gate electrode
21
. An active layer
15
is located over the gate electrode
21
and under the source and drain electrodes
17
and
19
. A first pixel-connecting line
25
a
, which is connected with one end of each respective pixel electrode
25
, electrically contacts the drain electrode
19
through a drain contact hole
35
, and is disposed parallel with the gate line
14
.
Still referring to
FIG. 1
, a plurality of common electrodes
23
are disposed parallel with the data line
13
and spaced apart from each other. One end of each common electrode
23
is electrically connected to the common line
12
, and the other end of each common electrode
23
contacts a common-connecting line
23
a
. A plurality of pixel electrodes
25
are disposed perpendicular to the first pixel-connecting line
25
a
, and communicate with the first pixel-connecting line
25
a
. The pixel electrodes
25
are spaced apart from each other and parallel with the adjacent common electrodes
23
. Moreover, each pixel electrode
25
corresponds to an adjacent common electrode
23
. The other ends of the pixel electrodes
25
are connected with a second pixel-connecting line
25
b
that is over the common line
12
. The second pixel-connecting line
25
b
overlaps a portion of the common line
12
such that a storage capacitor “C” is comprised of the common line
12
, the second pixel-connecting line
25
b
and an interposed dielectric layer. Although
FIG. 1
shows four common electrodes and three pixel electrodes, the number of the common and pixel electrodes depends on spaces between electrodes.
Still referring to
FIG. 1
, the gate and common lines
14
and
12
have a double-layer structure, respectively, in order to prevent signal delay of these lines. Moreover, the gate electrode
21
is also a double layer. Namely, the gate line
14
is comprised of first and second layers
14
a
and
14
b
and the common line
12
is also comprised of first and second layers
12
a
and
12
b
. The first layers
14
a
and
12
a
are usually a substance having low electrical resistance, such as Aluminum (Al). However, Aluminum is low in hardness and chemical resistance. So open-circuits and oxidation easily occur during an etching process. To overcome this problem, a second layer is formed on the first layer usually of a substance having high hardness and good chemical resistance, such as Molybdenum (Mo) or Chrome (Cr). Moreover, the first and second pixel-connecting lines
25
a
and
25
b
, and the pixel electrodes
25
are a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Each pixel electrode
25
is positioned between the common electrodes
23
so that each pixel and common electrodes
25
and
23
is arranged one after the other. The data line
13
and the source and drain electrodes
17
and
19
are made of the metallic material selected from a group consisting of chromium (Cr), aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), tantalum (Ta), tungsten (W), and antimony (Sb), and the like.
However, such a structure has a problem. During a patterning process of the data line
13
, the remains of the above-mentioned substance (Cr, Mo, Ta, W or the like) are left in step portions “A” around the common line
12
. These remains are not completely removed during the patterning process of the data line
13
, and exist in the capacitor “C” such that the short-circuit occurs between the data line
13
and the storage capacitor “C”.
FIGS. 2A
to
2
D are cross-sectional views taken alone lines II—II and III—III of FIG.
1
and illustrate fabricating processes for the array substrate.
Referring to
FIG. 2A
, the first gate line
14
a
(see
FIG. 1
) is formed on the substrate
11
by depositing and patterning a conductive metal having low electrical resistance, such as Aluminum (Al). The first gate electrode
21
a
that is extended from the first gate line is formed with the first gate line on the substrate
11
. Simultaneously, the first common line
12
a
is formed when the first gate line and the first gate electrode are formed. Thereafter, the second gate line
14
b
(see FIG.
1
), the second common line
12
b
and the second gate electrode
21
b
are formed on the respective first layers of these components by depositing and patterning the conductive metal having the high hardness and chemical resistance, such as Cr, Mo, or the like. Namely, the second gate line
14
b
(see
FIG. 1
) is formed to cover the first gate line
14
a
, the second common line
12
b
is formed to cover the first common line
12
a
, and the second gate electrode
21
b
is formed to cover the first gate electrode
21
a
. Thus, the double-layered gate
Booth Richard A.
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
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