Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-01-12
2001-02-27
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S612000
Reexamination Certificate
active
06194235
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to semiconductor manufacturing and more specifically to a method allowing for testing of an integrated circuit during an intermediate stage of its manufacture.
BACKGROUND OF THE INVENTION
Modern semiconductor integrated circuits, or “chips,” can be generally divided into two major categories: “microprocessors,” which perform logic operations and act generally as the “brains” of electronic systems incorporating them; and “memories,” which store data utilized by the microprocessor and other components of electronic systems. Traditionally, memory functions and microprocessing functions have been realized on separate chips. However, semiconductor manufacturers are currently pursuing “embedded” designs that incorporate both memory and microprocessor functions on the same chip. Embedded designs are advantageous because a single chip can take the place of separate memory and microprocessor chips, thus saving needed board space in a final computer product in which it is incorporated. Moreover, embedded chips are expected to produce cost savings, higher reliability, and faster speeds when compared to the use of separate memory and microprocessor chips.
However, the manufacture of embedded designs pose significant challenges. Significantly, the processes traditionally used to manufacture memories and microprocessors are different in ways that make their integration on a single chip difficult. For example, the process used to fabricate a Dynamic Random Access Memory (DRAM) cell array is typically quite different from the process used to fabricate the logic gates of a microprocessor. For example, while memories typically only require two metal levels of interconnections, the logic gates of microprocessor circuitry typically call for many more interconnect levels. Thus, the construction of the embedded memory array on a given portion of the embedded chip product will usually be complete at an intermediate stage of the embedded chip's manufacture. The remainder of the process is directed to the completion of the remaining interconnect levels necessary to complete the logic gates for the microprocessor portion of the chip.
However, because the embedded memory array is covered by the remaining levels used to complete the microprocessor portions of the embedded chip product, access to the array is limited, malking it difficult to directly test the memory using industry standard memory testing techniques. Moreover, the lack of direct array access makes it difficult to use known redundancy techniques to repair any defects within the embedded memory array.
The present inventions are directed to overcoming or at least reducing the effects of the one or more problems set forth above.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method for fabricating an integrated circuit is provided. The integrated circuit includes a surface, and the method comprises the steps of: forming a first layer on the surface; forming a second layer over the first layer; forming an opening in the second layer over the first layer; forming a third layer within the opening; forming a fourth layer over the second layer and over the third layer; removing the fourth layer which overlies the opening; removing the third layer from within the opening; and removing the first layer below the opening.
According to another aspect of the invention, a method for electrically testing an integrated circuit is provided. The integrated circuit includes a subcircuit which is operational at an intermediate stage during the processing of the integrated circuit, and the method comprises electrically testing the operational subcircuit during the intermediate stage.
REFERENCES:
patent: 5444000 (1995-08-01), Ohkubo et al.
patent: 6054334 (2000-04-01), Ma
Kress Hugh R.
Micro)n Technology, Inc.
Picardat Kevin M.
Winstead Sechrest & Minick P.C.
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