Method of fabricating an unlanded metal via of multi-level inter

Details Method of fabricating an unlanded metal via of multi-level inter Method of fabricating an unlanded metal via of multi-level inter

1997-12-19

1999-11-09

Hiteshen, Felisa

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438692, H01L 21302

Patent

active

059813954

ABSTRACT:
A method of fabricating an unlanded metal via of multi-level interconnection. The method is characterized by utilizing damascene scheme to form a metal wiring layer so that the processes are simplified. Moreover, by this method of the invention, a problem of difficulty in filling dielectric material between the metal wiring lines can be avoided and the metal layer does not have to be etched prior to filling the dielectric material. Further more, an etching stop layer is formed over the first inter-metal dielectric layer to avoid overetching during the formation of metal via, which therefore avoid short circuit. Forming the metal wiring lines by damascene scheme allows the etching stop layer to be easily formed over the first dielectric layer, without over etching the metal via.

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