Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2006-12-05
2006-12-05
Everhart, Caridad (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S773000, C257SE23141, C977S762000
Reexamination Certificate
active
07145246
ABSTRACT:
A method of forming a nanowire is disclosed. A nanowire having a first dimension is deposited on a first dielectric layer that is formed on a substrate. A sacrificial gate stack having a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over a first region of the nanowire leaving exposed a second region and a third region of the nanowire. A first spacer is deposited on each side of the sacrificial gate stack. A second dielectric layer is deposited over the first dielectric layer to cover the second region and the third region. The sacrificial gate stack is removed. The first region of the nanowire is thinned by at least one thermal oxidation process and oxide removal process to thin said first region from said first dimension to a second dimension.
REFERENCES:
patent: 5612255 (1997-03-01), Chapple-Sokol et al.
patent: 5858256 (1999-01-01), Minne et al.
patent: 6103540 (2000-05-01), Russell et al.
patent: 6342410 (2002-01-01), Yu
patent: 6562665 (2003-05-01), Yu
patent: 2003/0006410 (2003-01-01), Doyle
patent: 2004/0005258 (2004-01-01), Fonash et al.
patent: 2004/0136866 (2004-07-01), Pontis et al.
Fukuda, H., et al., “Fabrication Of Silicon Nanopillars Containing Polycrystalline Silicon/Insulator Multilayer Structures,” Appl. Phys. Lett. vol. 70, No. 3, Jan. 1997, pp. 333-335.
Takahashi, Akira, et al., “Si Single-Electron Transistors on SIMOX Substrates,” IEICE Electron, vol. E79-C, Nov. 11, 1996, pp. 1503-1508.
Tsutsumi, Toshiyuki, et al., “Close Observation of the Geometrical Features of an Ultranarrow Silicon Nanowire Device,” Japanese Journal of Applied Science, vol. 41, No. 6B, Part 1, Jun. 2002, pp. 4419-4422.
International Preliminary Report on Patentability, Chapter 1, International Application No. PCT/US2004/023569, mailed Feb. 9, 2006, 2 pages.
Written Opinion of The International Preliminary Examining Authority (IPEA), International Application No. PCT/US2004/023569, mailed Feb. 9, 2006, 5 pages.
Chau Robert
Hareland Scott A.
Blakely , Sokoloff, Taylor & Zafman LLP
Everhart Caridad
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