Method of fabricating an optical integrated circuit

Details Method of fabricating an optical integrated circuit Method of fabricating an optical integrated circuit

1999-06-24

2001-10-30

Gulakowski, Randy (Department: 1746)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Including integrally formed optical element

C216S024000

Reexamination Certificate

active

06309904

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating an optical integrated circuit comprising waveguides having different structures. The optical integrated circuit fabricated in accordance with the invention includes at least one BRS (Buried Ridge Stripe) waveguide which is etched and buried in a cladding layer and at least one ridge waveguide which is etched but not buried.
2. Description of the Prior Art
Optical integrated circuits are designed to combine a plurality of types of optical component having different structures and functions. Such circuits are made in two stages. In a first stage the various active and/or passive components are integrated on a substrate and butt coupled using a method well known to the skilled person. In a second stage the waveguides of the various components are etched in the form of stripes in order to assure lateral confinement of light.
The most widely used method for defining the waveguide stripes uses auto-alignment. For this, all the waveguides are etched simultaneously, in a single step, using a single mask.
This method is illustrated by
FIGS. 1A
to
1
D which are diagrammatic perspective views of an optical circuit at various stages of its fabrication. A BRS active waveguide
11
and a ridge passive waveguide
12
are integrated into the circuit.
In a first stage, a plurality of stacked layers of InP, for example, are deposited on a substrate
5
to form two portions
1
and
2
as shown in FIG.
1
A. The first portion
1
is for an active component, for example, and includes a guide layer
7
of quaternary material, for example InGaAsP, having a forbidden band width equivalent to 1.5 &mgr;m. The guide layer
7
is etched in the form of one or more stripes and then buried to form one or more BRS waveguides.
The second portion
2
is for a passive component, for example, and includes a guide layer
3
of quaternary material, for example InGaAsP, having a forbidden band width equivalent to 1.1 &mgr;m. The guide layer
3
is etched in the form of one or more stripes to form one or more ridge waveguides.
The two guide layers
3
and
7
of the two portions are butt coupled and encapsulated in a confinement layer
4
of InP, for example. The confinement layer
4
can be different in each portion. A conventional mask
9
defining the various waveguides to be produced is positioned on the confinement layer(s)
4
.
The next step, shown in
FIG. 1B
, consists in simultaneously or sequentially etching the two portions
1
and
2
on either side of the mask
9
to define the stripes of the various waveguides. In the example shown in
FIG. 1B
, the BRS waveguide
11
and the ridge waveguide
12
are etched in the form of respective single stripes. When etching is complete the mask
9
is removed.
When the stripe of each waveguide
11
and
12
has been defined, it is then necessary to be able to bury the BRS active guide
11
in a cladding layer without filling the etched part of the ridge waveguide
12
.
FIG. 1C
is a diagram illustrating this operation of encapsulating the BRS waveguide.
For this, a layer
8
of dielectric material, for example silica, is deposited onto the ridge stripe to protect it during subsequent epitaxial growth of a confinement layer
6
to bury the BRS guide. The confinement layer
6
is made of p-doped InP, for example. When the confinement layer
6
has been deposited, the silica protective layer
8
is removed and an optical integrated circuit
10
as shown in
FIG. 1D
is obtained, including a component with a buried BRS waveguide
11
and a component with a ridge waveguide
12
.
However, during epitaxial growth using the MOCVD (Metal Organic Chemical Vapor Deposition) process, excresences are formed in the transition area Z between the two portions
1
and
2
. These excresences can have a size of up to several microns, typically being more than 4 &mgr;m thick and more than 300 &mgr;m wide.
During epitaxial growth the circuit is heated by infrared lamps. This heating causes decomposition of the reactants on or near the surfaces followed by a phenomenon of nucleation. This nucleation does not occur on the dielectric material (silica, for example) and so the InP layer deposited epitaxially cannot grow on the silica protective layer
8
. Consequently, all the elements on top of the layer
8
diffuse into and coalesce in the transition area Z on the InP material of the confinement layer
6
being formed. All of the material that should have been grown on the silica therefore ends up in the transition area Z, which causes the excresences to appear, their size depending on the size of the surfaces protected by the silica layer
8
.
These excresences interfere with subsequent circuit fabrication operations. Lithographic steps in particular and ion implantation of the cladding layer to obtain lateral insulation are particularly difficult to carry out on the circuit because of the presence of these excresences. Also, a differential thickness is created along the BRS active waveguide stripe which can cause malfunctions of the waveguide.
Also, protecting the ridge guide
3
with silica implies migration of P and/or As from the waveguide
3
toward the dielectric silica layer
8
, which degrades the performance of the waveguide and therefore of the optical component
2
.
Another approach to making an optical integrated circuit comprising at least one BRS waveguide and one ridge waveguide consists in using the realignment method well known to the skilled person and illustrated in
FIGS. 2A
to
2
D. After depositing a plurality of layers onto a substrate
5
to form two portions
1
and
2
each having a respective guide layer
7
and
3
(see FIG.
2
A), a mask
9
is placed on the top confinement layer
4
. The shape of this mask is such that it covers all of the surface of the portion
2
, which is for a passive ridge guide, for example, and defines the design of the waveguide stripe of the portion
1
to be etched to obtain a BRS active guide, for example.
Accordingly, in a first step, only the BRS waveguide
11
is etched (FIG.
2
B). Then, after removing the mask
9
, a confinement layer
6
of p-doped InP, for example, is grown epitaxially over all of the surface of the circuit (FIG.
2
C).
The final step, represented in
FIG. 2D
, then consists in protecting the first active component, including the BRS guide
11
formed in this way, with another mask and then etching the second portion
2
, using an appropriate mask, to define the ridge stripe
12
. However, the InP layer to be etched in order to etch the ridge stripe is very thick since it comprises the protective layer
4
and the layer
6
deposited during epitaxial growth. The total thickness to be etched to form the ridge stripe is typically at least 5 &mgr;m, compared with approximately 2 &mgr;m when the auto-alignment method is used. The ridge stripe obtained (
FIG. 2D
) is therefore fragile and breaks easily when cleaving the components, making it very difficult or even impossible to achieve good optical coupling.
One solution to the problem of avoiding this fragility of the ridge stripe is not to deposit any confinement layer
4
on the guide layer
3
of the portion
2
for the ridge guide, or at least to reduce the thickness of the confinement layer
4
. In this case, the layer
6
of p-doped InP deposited during epitaxial growth is in direct contact with (or near) the ridge waveguide
3
. The ridge waveguide
3
being passive in this example, it does not amplify the light signal and the p-doped InP causes greater propagation losses. This solution therefore degrades the performance of the passive component
2
with the ridge guide and therefore cannot be used to fabricate optical integrated circuits.
One aim of the invention is therefore to fabricate an optical integrated circuit comprising at least one BRS waveguide and at least one ridge waveguide which are butt coupled and defined by the auto-alignment method without creating excresences in the transition area between the two types of guide.
SUM

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