Method of fabricating an isolation structure on a semiconductor

Details Method of fabricating an isolation structure on a semiconductor Method of fabricating an isolation structure on a semiconductor

1998-02-11

2000-08-29

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438702, H01L 21762

Patent

active

061107980

ABSTRACT:
A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

REFERENCES:
patent: 4222792 (1980-09-01), Lever et al.
patent: 4361600 (1982-11-01), Brown
patent: 4407851 (1983-10-01), Kurosawa et al.
patent: 4604162 (1986-08-01), Sobczak
patent: 4615746 (1986-10-01), Kawakita et al.
patent: 4689872 (1987-09-01), Appels et al.
patent: 4735821 (1988-04-01), Yamazaki et al.
patent: 4814287 (1989-03-01), Takemoto et al.
patent: 4845048 (1989-07-01), Tamaki et al.
patent: 4974060 (1990-11-01), Ogasawara
patent: 5084130 (1992-01-01), Yamazaki et al.
patent: 5176789 (1993-01-01), Yamazaki et al.
patent: 5214603 (1993-05-01), Dhong et al.
patent: 5331197 (1994-07-01), Miyawaki et al.
patent: 5336629 (1994-08-01), Dhong et al.
patent: 5453396 (1995-09-01), Gonzalez et al.
patent: 5629539 (1997-05-01), Aoki et al.

Affiliated with

Also associated with

Rating

Method of fabricating an isolation structure on a semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating an isolation structure on a semiconductor , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating an isolation structure on a semiconductor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1249240