Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-12-17
2001-07-03
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S444000
Reexamination Certificate
active
06255191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a semiconductor fabrication method for fabricating an isolation structure, including an STI (shallow-trench isolation) structure, in an integrated circuit (IC).
2. Description of Related Art
Device Isolation Technology is an important process in IC fabrication for electrically isolating the various active components in the IC. As integration becomes higher, isolation becomes more difficult. A conventional method for device isolation is the so-called Local Oxidation of Silicon (LOCOS) technique, which is used to provide field oxide layers to serve as isolation structures in the integrated circuit. One drawback to the LOCOS technique, however, is that the resulting isolation structure has a bird's beak shape that makes the further downsizing of the IC device difficult to realize. The STI (shallow trench isolation) technique serves as a solution to the drawback of the LOCOS technique, and which is now widely used in sub-half micron semiconductor fabrication.
A conventional method for fabricating an STI structure in an integrated circuit is illustratively depicted in the following with reference to
FIGS. 1A-1E
.
Referring first to
FIG. 1A
, in the initial step, a semiconductor substrate
10
, such as a silicon substrate is prepared. A pad oxide layer
20
is then formed over the substrate
10
. Next, a layer of silicon nitride
30
is formed over the pad oxide layer
20
. After this, a photoresist layer
40
is coated over the silicon nitride layer
30
and then selectively removed to serve as an etching mask. Then, with the photoresist layer
40
serving as mask, an anisotropic etching process is performed to etch away the unmasked portions of the silicon nitride layer
30
, the pad oxide layer
20
, and the substrate
10
until reaching a predefined depth into the substrate
10
, whereby a plurality of trenches
50
are formed in the substrate
10
. After this, the photoresist layer
40
is removed.
Referring next to
FIG. 1B
, in the subsequent step, a thermal oxidation process is performed to cause the growth of a thin liner oxide layer
60
over all the exposed surfaces of the substrate
10
in the trenches
50
, but not filling up the trenches
50
. Next, an APCVD (atmospheric-pressure chemical-vapor deposition) process is performed to deposit silicon oxide into the trenches
50
and over the silicon nitride layer
30
to thereby form a silicon oxide layer
70
. Then, a densification process is performed to densify the silicon oxide layer
70
by heating the wafer at a temperature of about 1,000° C. for a duration of from about 10 to 30 minutes.
Referring further to
FIG. 1C
, in the subsequent step, a CMP (chemical-mechanical polishing) process is performed on the silicon oxide layer
70
to remove an upper part of the silicon oxide layer
70
until exposing the silicon nitride layer
30
. Through this process, only those portions of the silicon oxide layer
70
that lie in the trenches
50
(
FIG. 1A
) remain. These remaining portions of the silicon oxide layer
70
are herein and hereinafter designated by the reference numeral
80
and referred to as oxide plugs. One drawback to the use of the CMP process, however, is that the top surface of the oxide plugs
80
are slightly recessed to form a dished surface, as indicated by the reference numeral
90
, due to the reason that the silicon oxide plugs
80
are less rigid than the silicon nitride layer
30
.
Referring further to
FIG. 1D
, in the subsequent step, the silicon nitride layer
30
is entirely etched away by using a suitable etchant, such as hot phosphate solution. After this is done, the top surface of the pad oxide layer
20
is exposed and is lower than the top surface of the oxide plugs
80
.
Referring further to
FIG. 1E
in the subsequent step, hydrofluoric acid (HF) is used as an etchant to etch away the entire pad oxide layer
20
and an upper part of the oxide plugs
80
. Through this process, the top surface of the oxide plugs
80
is substantially leveled to the top surface of the substrate
10
. The remaining oxide plugs
80
and the underlying liner oxide layer
60
in the trenches
50
(
FIG. 1A
) in combination constitute an STI structure. The resulting STI structure, however, is formed with undesirable recessed portions, as demonstratively illustrated and indicated by the reference numeral
100
in FIG.
1
E. This is because the HF solution etches into the oxide plugs
80
more rapidly than into the pad oxide layer
20
, and also the top surface of the oxide plugs
80
is higher than the top surface of the pad oxide layer
20
, thus causing the edge part of the oxide plugs
80
to be overly etched and thereby form the recessed portions
100
.
In practice, the foregoing conventional method has the following three major drawbacks. First, in the densification process to densify the silicon oxide layer
70
, since the entire wafer, not just the silicon oxide layer
70
, is subject to the high-temperature condition at about 1,000° C., the wafer surface may be warped due to the various component layers in the wafer having different thermal expansion coefficients (the thermal expansion coefficients of silicon nitride, silicon, and silicon oxide are respectively 3.5×10
−6
/° C. 2.6×10
−6
/° C., and 0.5×10
−6
/° C.). Therefore, during the heat treatment, the silicon nitride layer
30
expands more rapidly than and thus stresses the silicon substrate
10
and the silicon oxide layer
70
. This may cause structural defects to the wafer, making the resultant IC device unreliable to use.
Second, in the CMP process subsequent to the densification process, since the silicon dioxide plug
80
is less rigid than the silicon nitride layer
30
and the polishing force is consistently applied on all surface parts of the wafer, the resulting oxide plugs
80
may be undesirably formed with the dished surface
90
. Moreover, since the polishing force is typically set to suit the silicon nitride layer
30
, it can scratch the surface of the oxide plugs
80
; consequently, in the subsequent metallization process, some polysilicon can be left in the scratches in the surface of the oxide plugs
80
, thus electrically bridging the insulating oxide plugs
80
to other components in the integrated circuit.
Third, the recessed portions
100
in the edges of the oxide plugs
80
, if too deeply formed into the oxide plugs
80
, may cause a kink effect in the subsequently formed transistors, thus deviating the subthreshold current of these transistors. This can make the transistors inoperable.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating an isolation structure, including an STI structure, in an integrated circuit, which is free from the above-mentioned three drawbacks of the prior art.
In accordance with the foregoing and other objectives of the present invention, a new method for fabricating an STI structure in an integrated circuit is provided. By the method of the invention, the first step is to prepare a semiconductor substrate, and then an adhesive layer a hard mask layer, and an etch-end layer are successively formed over the substrate. Next, a selective etching process is performed to etch away selected portions of the etch-end layer, the hard mask layer, and the adhesive layer, but not exposing the substrate, to thereby form a first opening and a second opening in the etch-end layer and the hard mask layer above the adhesive layer. The first opening is larger in dimension than the second opening. After this, a first sidewall spacer is formed on the sidewall of the first opening while a second sidewall spacer is formed on the sidewall of the second opening in such a manner that the adhesive layer at the bottom of the first opening that is uncovered by the first sidewall spacer is entirely removed to expose the underlying part of the substrate, while the adhesive layer at
Gau Jing-Horng
Huang Hsiu-Wen
Chaudhuri Olik
Duy Mai Anh
Huang Jiawei
Patents J.C.
United Microelectronics Corp.
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