Method of fabricating an integrated circuit with lines of critic

Details Method of fabricating an integrated circuit with lines of critic Method of fabricating an integrated circuit with lines of critic

1992-12-31

1994-08-02

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437 48, 437 52, 437186, 437228, 437233, H01L 21285

Patent

active

053345410

ABSTRACT:
A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connection between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

REFERENCES:
patent: 4416049 (1983-11-01), McElroy
patent: 4554729 (1985-11-01), Tanimura et al.
patent: 4794561 (1988-12-01), Hsu
patent: 5087537 (1992-02-01), Conway et al.
Chien et al., "Characterization of stepper-lens Aberrations and critical dimension control", SPIE, vol. 538 Optical microlithography IV (1985), pp. 197-206.

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