Method of fabricating an integrated circuit voltage multiplier c

Details Method of fabricating an integrated circuit voltage multiplier c Method of fabricating an integrated circuit voltage multiplier c

1982-08-23

1983-12-13

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, 29 2542, 148187, 148188, 357 51, 357 59, H01L 2198

Patent

active

044198124

ABSTRACT:
Disclosed is a process which is fully compatible with normal two layer polysilicon SNOS process and provides polysilicon parallel plate capacitors and silicon gate non-memory MOS transistors (diodes) for constructing therefrom an on-chip, dual polarity high voltage multiplier. From the polysilicon I layer deposited over a gate oxide, the polysilicon I resistor, the non-memory device gate and the capacitor lower plate are formed. Then, the resistor, non-memory device gate and active region and the periphery of the capacitor lower plate are covered with an isolation oxide. Next, a dielectric, e.g., oxide-nitride, and polysilicon II layers are formed over the structure. Polysilicon II is patterned into interconnect, gate for SNOS memory device and capacitor upper plate, the latter having a plurality of holes therein. The dielectric is formed into SNOS device gate insulator and the capacitor insulator, the latter having holes in registration with the holes in the capacitor upper plate. Finally, by thermal diffusion of active impurities, all gates, interconnect and both capacitor plates are doped and all sources and drains for memory and non-memory devices formed.

REFERENCES:
patent: 3860836 (1975-01-01), Pederson
patent: 3864817 (1975-02-01), Lapham, Jr. et al.
patent: 4115795 (1978-09-01), Masuoka et al.
patent: 4240092 (1980-12-01), Kuo
patent: 4249194 (1981-02-01), Rogers
"On-Chip High-Voltage Generation in MNOS Integrated Circuits Using Improved Voltage Multiplier Technique", by J. F. Dickson, IEEE Journal of Solid State Circuits, vol. SC 11, No. 3, Jun. 1976, pp. 374-378.

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