Method of fabricating an insulated gate semiconductor device hav

Details Method of fabricating an insulated gate semiconductor device hav Method of fabricating an insulated gate semiconductor device hav

1988-03-23

1990-07-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 57, 437162, 437193, 437913, 437 44, 437200, 357 239, 357 42, 357 59, H01L 21265, H01L 21283

Patent

active

049391542

ABSTRACT:
The present invention provides a fabrication method of miniature insulated gate semiconductor devices such as MOS and CMOS in which their gates are formed by self-alignment, and in addition, provision of lightly doped drain (LDD) structure is easy. Therefore the present invention is extremely effective in the fabrication of miniature semiconductor devices which can be highly integrated and can operate at high speed.

REFERENCES:
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4378627 (1983-04-01), Jambotkar
patent: 4414737 (1983-11-01), Menjo et al.
patent: 4419810 (1983-12-01), Riseman
patent: 4471522 (1984-09-01), Jambotkar
patent: 4691435 (1987-09-01), Anantha et al.
Huang et al., "A MOS Transistor With Self-Aligned Polysilicon Source-Drain", IEEE Electron Device Letts., vol. EDL-7, No. 5, May 1986, pp. 314-316.
Oh et al., "A New MOSFET Structure With Self-Aligned Polysilicon Source and Drain Electrodes", IEEE Electron Device Letts., vol. EDL-5, No. 10, Oct. 1984, pp. 400-402.

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