Method of fabricating an insulated gate semiconductor device

Details Method of fabricating an insulated gate semiconductor device Method of fabricating an insulated gate semiconductor device

1994-03-22

1995-09-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 6, 437 40, 437 44, 437 29, H01L 21265, H01L 4900

Patent

active

054515319

ABSTRACT:
An improved insulated gate semiconductor device comprises a high-concentration p-type semiconductor region formed widely enough to protrude over n-type emitter regions without reaching an n-type epitaxial layer over a p-type base region only in first regions wherein the n-type emitter regions are wider than second regions as viewed from the top of the device. A gate threshold voltage V.sub.GE (th) has a relatively high level V.sub.GE (th-High) in the first regions, so that a low collector-emitter saturation voltage V.sub.CE (sat) and a low saturation current I.sub.CE (sat) are achieved. This provides for a high short-circuit tolerance as well as a high latch-up tolerance with low losses.

REFERENCES:
patent: 4774198 (1988-09-01), Contiero et al.
patent: 4971921 (1990-11-01), Fukunaga et al.
patent: 5023191 (1991-06-01), Sakurai
patent: 5034336 (1991-07-01), Seki
patent: 5164327 (1992-11-01), Maruyama
patent: 5234851 (1993-08-01), Korman et al.

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