Method of fabricating an insulated gate semiconductor device

Details Method of fabricating an insulated gate semiconductor device Method of fabricating an insulated gate semiconductor device

1994-01-04

1994-12-13

Thomas, Tom

Fishing, trapping, and vermin destroying

437 45, 437150, H01L, H01L

Patent

active

053729609

ABSTRACT:
An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.

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C. F. Codella et al., "Submicron IGFET Device with Double Implanted Lightly Doped Drain/Source Structure," IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6584-6586.

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