Method of fabricating an insulated-gate bipolar transistor

Details Method of fabricating an insulated-gate bipolar transistor Method of fabricating an insulated-gate bipolar transistor

1995-04-03

1996-07-30

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 6, 437 40, 437 41, 437974, 148DIG126, H01L 21265

Patent

active

055411223

ABSTRACT:
A method of fabricating a fast-switching, low-R(on) insulated-gate bipolar transistor including providing an N-type semiconductor wafer with a planar surface, forming a thin heavily-doped layer, having a concentration in the range of 3.times.10.sup.17 /cm.sup.3 to 1.times.10.sup.19 /cm.sup.3, in the wafer adjacent the planar surface, providing a P-type semiconductor wafer, and bonding a surface of the P-type wafer to the planar surface of the N-type wafer. An emitter and a gate are then formed in the N-type wafer in the usual manner and a collector is formed on the P-type wafer.

REFERENCES:
patent: 5141887 (1992-08-01), Liaw et al.
patent: 5141889 (1992-08-01), Terry et al.
A. Nakagawa et al., "1800V Bipolar-Mode MOSFETs: a First Application of Silicon Wafer Direct Bonding (SDB) Technique to a Power Device," 1986 IEEE IEDM Technical Dig., pp. 122-125.
H. Ohashia et al., "Study of Si-Wafer Directly Bonded Interface Effect on Power Device Characteristics," 1987 IEEE IEDM Technical Dig., pp. 678-681.
D. Kuo et al., "Optimization of Epitaxial Layers for Power Bipolar-MOS Transistor," IEEE Electron Device Letters, vol. EDL-7, No. 9, Sep. 1986, pp. 510-512.
B. Baliga et al., "The Insulated Gate Rectifier (IGR): a New Power Switching Device," 1982 IEEE IEDM, pp. 264-267.
J. Russell et al., "The Comfet--A New High Conductance MOS-Gates Device," IEEE Electron Device Letters, vol. EDL-4, No. 3, Mar. 1983, pp. 63-65.

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