Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-07-14
2001-03-27
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S398000, C438S254000, C438S255000
Reexamination Certificate
active
06207526
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing processes, and more specifically, to a method of fabricating a self-aligned crown-shaped rugged capacitor for high density DRAM (dynamic random access memory) cells.
BACKGROUND OF THE INVENTION
In the electric industry, memory devices are of vital application in various kinds of computer, communication, and consumer electronic products. In the electric equipment, memory devices are employed for the storage and exchange of operating data and information. The information can be stored temporarily or permanently in various kinds of memory devices, depending on the system design and needs. The DRAM is one of the most important memory devices for providing temporary data storage in numerous system applications. In the last decade, the DRAM has become the flagship product of the semiconductor industry for its high-density structure and wide applications.
In general, a DRAM cell is composed of a transistor and a capacitor. A MOSFET (metal oxide semiconductor field effect transistor) is utilized preferably to enable the writing and the reading of the data. The capacitor is employed to store electric charge, wherein the data is represented by the voltage level of the electric charge. The DRAM cells can be accessed with unlimited reading and writing cycles with high frequency and reliability.
For reducing the cost and increasing the competitive power of the DRAM devices, the density of DRAM cells on a unit of chip area must be raised continuously. The number of DRAM cells on each chip has increased from 16M to 64M and it is believed that the 256M and higher volume DRAM chips will become the most competitive products before the end of the twentieth century. With the fast increasing density, the area occupied by each DRAM cell with a transistor and a capacitor has to narrow down several times while providing the same function and operation on data storage and exchange.
However, since the storage capacity of a capacitor is proportional to the surface area of the electrode, the capacitor structure of the traditional plate electrode must be improved. The capacitor structure must be redesigned to provide raised storage capacity or the capacitance under per unit chip area. In prior art designs, various types of stacked-capacitor structure have been proposed. As an example, M. Sakao et al. proposed a capacitor-over-bit-line (COB) cell structure in their work “A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs” (in IEDM Tech. Dig., p. 655, 1990). It is disclosed in this reference that three-dimensional memory cells, such as stacked or trench capacitor cells, are necessary for future DRAMs in order to obtain sufficient storage capacitance in a small area. Several stacked capacitor cells have been proposed for 64 Mb DRAMs, because, as compared to trench capacitor cells, their fabrication procedure is relatively simple and they offer higher immunity to soft error. In the stacked capacitor cell, large capacitance can be obtained by increasing storage node height, but this causes difficulties with optical delineation and patterning. Three dimensionally arranged storage node structures have been proposed. However, the attempts cause difficulties in the fabrication procedure.
H. Wantanabe et al. disclosed a new cylindrical capacitor structure in their work “A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256 Mb DRAMs” (in IEDM Tech. Dig., p.259, 1992). A new selective etching technique using a low-pressure vapor hydrogen fluoride is developed to form the cylindrical capacitor electrode. A high selective etching (2000 times) of borophospho-silicate-glass to SiO
2
is realized with the technique. Disilane molecule irradiation in ultra-high vacuum chamber achieves the HSG-Si formation on the whole surface of phosphorous doped amorphous Si cylindrical electrode.
However, conventional stacked-capacitor structures have some unsolved strength problem in the fabrication of three-dimensional electrodes. In general, most of the three dimensional electrode structure are composed of several silicon layer which are deposited and defined separately. The three-dimensional structures with interfaces of several deposition processes on a single node are found to suffer from defect issues like cracks. The problem greatly damages the yield of the process. In addition, for developing future high density DRAMs, the conventional stacked-capacitor structure cannot get sufficient capacitance. What is needed in the field is an improved design of a capacitor cell structure with raised storage capacitance without strength problems such as the crack issue during manufacturing processes.
SUMMARY OF THE INVENTION
The present invention discloses a method of fabricating a storage cell as a capacitor. An extended self-aligned crown-shaped rugged capacitor for high density DRAM cells can be formed without the prior art crack issue. One of the advantages of the method provided in the invention is that the storage cell can be formed with reduced processing steps by the self-aligned approach in the present invention. The self-aligned process in forming capacitor contact opening can be integrated into the semiconductor process of forming high-density DRAM cells. The capacitor structure having extended upper crown regions formed by the proposed method can provide improved capacitance than conventional stacked-capacitor structure. The number of masks used can also be reduced with the self-aligned process in providing the base structure of the capacitor node with improved strength and reliability.
The method of the present invention for forming a capacitor on a semiconductor substrate includes the following steps. At first, a first oxide layer is formed over the substrate and a nitride layer is then formed over the oxide layer. A second oxide layer is formed over the nitride layer and a first silicon layer is formed over the second oxide layer. Next, a node opening is defined in the first silicon layer, the second oxide layer, and the nitride layer, upon the first oxide layer. Sidewall structures are then formed on sidewalls of the node opening.
A contact opening is then defined in the first oxide layer under the node opening. The contact opening is defined in the first oxide layer under a region uncovered by the sidewall structures. The sidewall structures and a portion of the nitride layer nearby the node opening are removed to form undercut structures under the second oxide layer. A second silicon layer is then formed conformably over the contact opening, the undercut structures, the node opening, and the first silicon layer. A node-top defining layer is formed on the second silicon layer and is patterned to leave a node-top defining region. Next, a portion of the second silicon layer and a portion of the first silicon layer uncovered by the node-top defining region are removed. Silicon sidewalls are formed on sidewalls of the node-top defining region, and are communicated to the first silicon layer and the second silicon layer to form an electrode. The node-top defining region, the second oxide layer, and the nitride layer are removed. A wet etch is performed to remove the nitride layer and to roughen the surface of the electrode. A dielectric film is then formed conformably over the electrode. Finally, a conductive layer is formed over the dielectric layer.
In the illustrative examples of the present invention, a wet etch process is employed and preferably applied to roughen the surface of the electrode. In the preferred embodiments, the wet etch is carried out with a hot phosphoric solution to remove the remaining silicon nitride layer, and also to remove part of the surface portion of the electrode of silicon material, in order to roughen the surface of the electrode for having a rugged surface. Therefore, a greatly raised capacitance is provided by the rugged structure of the bottom electrode.
REFERENCES:
patent: 5554557 (1996-09-01), Koh
patent: 6080633 (2000-06-01), Sze et al.
Abbott Barbara E.
Acer Semiconductor Manufacturing Corp.
Fourson George
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