Method of fabricating an EPROM with high voltage transistors

Details Method of fabricating an EPROM with high voltage transistors Method of fabricating an EPROM with high voltage transistors

1995-08-28

1997-10-07

Niebling, John

Fishing, trapping, and vermin destroying

437 43, 437 52, H01L 218247, H01L 21265

Patent

active

056747624

ABSTRACT:
A method of fabricating an integrated circuit (272) having memory, logic, high voltage, and high current functionality uses a modular implant process step (104) to form a drain extension region (204), a source extension region (205), and a base extension region (206) in a substrate (200). The dopants from the modular implant process step (104) are later diffused into the substrate (200) during a LOCOS process step (105). A modular gate oxide formation step (111) produces three different thicknesses of gate oxides (309, 311, 312) which provide ultra high voltage, high voltage, and low voltage functionality for the integrated circuit (272).

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