Method of fabricating an encapsulant lock feature in...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support

Reexamination Certificate

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C438S126000, C438S127000, C438S622000, C029S841000, C029S855000, C029S856000

Reexamination Certificate

active

06423581

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor die encapsulation and, more particularly, to an encapsulation scheme that provides for improved adhesion of the encapsulant to an underlying printed circuit board.
Plastic encapsulates are commonly used in integrated circuit packaging to protect the integrity of the encapsulated semiconductor die and the associated electrical connections. U.S. Pat. No. 5,701,034 (Marrs) is directed to providing improved encapsulation of a semiconductor die and teaches the formation of a locking moat in a heat sink to which the semiconductor die is coupled. The encapsulant material is cured in the locking moat of the heat sink and about the semiconductor die to interlock the encapsulant and the heat sink. The teachings of U.S. Pat. No. 5,701,034 are not, however, related to improving adhesion or coupling of the encapsulant to resin laminates commonly utilized to form printed circuit boards. Further, the design of the locking moats and the structure of the heat sink in the '034 patent do not complement each other to provide for an efficient method of manufacture.
In many instances, a semiconductor die is positioned on the upper surface of a printed circuit board substrate and an encapsulant is arranged to cover the semiconductor die, portions of the upper surface of the substrate, and any leads, bond pads, or other bonding locations on the upper surface of the substrate. Robust encapsulant-to-substrate adhesion is critical in this type of structure because the encapsulant contacts only the upper surface of the substrate, as opposed to completely surrounding the substrate and die.
In practice, encapsulant-to-substrate adhesion is limited by specific design constraints. For example, the upper surface of the substrate typically includes conductive portions and solder resist portions. It is often difficult to identify a suitable encapsulant that bonds equally well to the conductive portions and the solder resist portions. Further, the encapsulant material must also be selected to minimize the deleterious effects of particulate matter contaminating the surface of the substrate. All of these design considerations limit the ability to achieve sufficient encapsulant-to-substrate adhesion.
Accordingly, there is a need for a semiconductor die encapsulation scheme that provides for optimum encapsulant-to-substrate adhesion while accounting for variations in the composition of the substrate surface and for the deleterious effects of particulate matter on the surface of the substrate, particularly where the substrate involved is a printed circuit board laminate. Further, there is a need in the art for an encapsulation scheme that is directed to improving adhesion or coupling of the encapsulant to the resin laminates commonly utilized to form printed circuit boards.
BRIEF SUMMARY OF THE INVENTION
This need is met by the present invention wherein a void is formed in the structure of a laminate supporting a semiconductor die and where an encapsulant is arranged to encapsulate the semiconductor die and fill the void in the laminate.
In accordance with one embodiment of the present invention, a packaged semiconductor device is provided comprising a semiconductor chip, a laminate, and an encapsulant. The laminate defines first and second major faces and includes an electrically conductive layer, an underlying substrate supporting the electrically conductive layer, and at least one void formed in the laminate so as to extend from one of the major faces through the electrically conductive layer at least as far as the underlying substrate. The encapsulant is positioned to mechanically couple the semiconductor die to the laminate to extend into the void so as to contact the underlying substrate.
The void or voids preferably extend into the underlying substrate and may extend from the first major face through the electrically conductive layer and the underlying substrate to the second major face. The contact between the encapsulant and the underlying substrate is preferably characterized by an adhesive bond and the encapsulant preferably occupies substantially all of the void.
In accordance with another embodiment of the present invention, a packaged semiconductor device is provided comprising a semiconductor chip, a laminate, and an encapsulant. The laminate defines first and second major faces and includes a solder resist layer, an underlying substrate, an electrically conductive layer interposed between the solder resist layer and the underlying substrate, and at least one void formed in the laminate so as to extend from one of the major faces through the solder resist layer and the electrically conductive layer at least as far as the underlying substrate. The encapsulant is positioned to mechanically couple the semiconductor die to the laminate and to extend into the void so as to contact the underlying substrate.
In accordance with yet another embodiment of the present invention, a packaged semiconductor device is provided comprising a semiconductor chip, a laminate, and an encapsulant. The laminate defines first and second major faces and includes a plurality of laminated layers. The laminate also includes at least one void formed therein so as to extend from one of the major faces through a plurality of the laminated layers. The encapsulant is positioned to mechanically couple the semiconductor die to the laminate and is further positioned to extend into the void across the plurality of laminated layers so as to contact a portion of the laminate between the first and second major faces of the laminate.
In accordance with yet another embodiment of the present invention, a packaged semiconductor device is provided comprising a semiconductor chip, a prepreg epoxy resin glass-cloth laminate, and an encapsulant. The prepreg epoxy resin glass-cloth laminate defines first and second major faces and includes a plurality of laminated prepreg layers and at least one void formed therein so as to extend from one of the major faces through a plurality of the laminated prepreg layers. The encapsulant is positioned to mechanically couple the semiconductor die to the prepreg epoxy resin glass-cloth laminate and to extend into the void across the plurality of laminated prepreg layers so as to contact a portion of the laminate between the first and second major faces of the laminate.
In accordance with yet another embodiment of the present invention, a packaged semiconductor device is provided comprising a semiconductor chip, a laminate, and an encapsulant. The laminate defines first and second major faces and includes a plurality of laminated layers and at least one void formed therein so as to extend from one of the major faces through a plurality of the laminated layers. The void is characterized by a profile that varies across adjacent laminated layers. The encapsulant is positioned to mechanically couple the semiconductor die to the laminate and to extend into the void across the varying profile so as to contact a portion of the laminate between the first and second major faces of the laminate. The varying profile may be characterized by a cross-sectional area that changes from a first value in a selected laminated layer to a second value in an adjacent laminated layer. The second value is preferably larger than the first value.
In accordance with yet another embodiment of the present invention, a packaged semiconductor device is provided comprising a semiconductor chip, a laminate, and an encapsulant. The laminate defines first and second major faces and includes a plurality of laminated layers, including a selected laminated layer and an adjacent laminated layer. The selected laminated layer is disposed closer to the first major face than the adjacent laminated layer. The laminate includes at least one void formed therein so as to extend from the first major face through the selected laminated layer and into the adjacent laminated layer. The void is characterized by a varying profile that defines a ledge portion in the selected laminated layer

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