Method of fabricating an ASIC cell having multiple contacts

Details Method of fabricating an ASIC cell having multiple contacts Method of fabricating an ASIC cell having multiple contacts

1992-08-31

1995-10-03

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 51, 437250, H01L 21265

Patent

active

054551919

ABSTRACT:
A high density ASIC cell provides customization solely at the polysilicon #2, insulator #3 levels. High density is achieved by permitting a metal #1 trace to traverse an underlying transistor, without requiring space between adjacent transistors to facilitate traversing interconnects. Oversized collector and emitter traces at the polysilicon #1 level make downward contact with the collector and base regions of the underlying transistor, and provide redundant upward contact with collector and emitter polysilicon #2 traces. Contact between the transistor base and a base polysilicon #2 trace is also made. The polysilicon #2 emitter, base and collector traces provide a replicated, unvarying pattern that preferably defines a 3.times.3 matrix of potential contact points for overlying metal #1 traces to contact the underlying transistor's emitter, base and collector. A metal #1 trace can traverse this 3.times.3 matrix simply by not providing openings in the insulating #3 layer beneath the traverse. If a metal #1 trace is to contact a region of the underlying transistor, an opening is made in the insulation #3 layer over the necessary contact in the 3.times.3 matrix at the polysilicon #2 level. Thus, customization of the ASIC is made at the metal #1 level, and at the insulation #3 level by determining which metal #1 traces will contact what regions of the underlying transistor.

REFERENCES:
patent: 4884118 (1989-11-01), Hui et al.
patent: 5111273 (1992-05-01), Orbach et al.
patent: 5208178 (1993-05-01), Usami

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