Method of fabricating a wafer probe card for testing an integrat

Details Method of fabricating a wafer probe card for testing an integrat Method of fabricating a wafer probe card for testing an integrat

1995-06-06

1997-06-17

Fourson, George

Etching a substrate: processes

Forming or treating electrical conductor article

Forming or treating lead frame or beam lead

437217, 437220, 324765, H01L 23485

Patent

active

056393857

ABSTRACT:
One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed. The present invention further provides a wafer probe card which includes a multi-layer, relatively flexible tape-like substrate having a first conductive layer patterned to have a number of probe leads thereon. The first conductive layer of probe leads are formed on an insulating layer having an inner peripheral edge defining a central opening in which an IC die is placed for testing. The insulating layer further includes inner and outer peripheral openings therethrough and a second conductive layer is provided on a side of the insulating layer opposite the probe leads. Inner and outer edge portions of the second conductive layer are exposed through the inner and outer peripheral openings, respectively. Selected probe leads are cut at an edge of the inner and outer peripheral openings in the insulating layer, bent past the insulating layer and bonded to the exposed inner and outer edge portions of the second conductive layer.

REFERENCES:
patent: 4064552 (1977-12-01), Angelucci et al.
patent: 4413404 (1983-11-01), Burns
patent: 4801999 (1989-01-01), Hayward et al.
patent: 4997517 (1991-03-01), Parthasarathi
patent: 5025114 (1991-06-01), Braden
patent: 5196725 (1993-03-01), Mita et al.
patent: 5221858 (1993-06-01), Higgins, III
patent: 5231556 (1993-07-01), Shimizu et al.
patent: 5231756 (1993-08-01), Tokita et al.
patent: 5235209 (1993-08-01), Shimizu et al.
patent: 5355105 (1994-10-01), Angelucci
patent: 5399809 (1995-03-01), Takenouchi

Affiliated with

Also associated with

Rating

Method of fabricating a wafer probe card for testing an integrat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a wafer probe card for testing an integrat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a wafer probe card for testing an integrat will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2155386