Method of fabricating a voidless IC electrical plug

Details Method of fabricating a voidless IC electrical plug Method of fabricating a voidless IC electrical plug

1996-08-02

1998-04-14

Niebling, John

Fishing, trapping, and vermin destroying

437195, 437203, H01L 2144

Patent

active

057390479

ABSTRACT:
A method of fabricating a IC electrical plug, which removes an overhang to prevent formation of voids inside the plug. A transistor with a gate and source/drain terminals is formed on a silicon substrate. A dielectric layer is formed above the silicon substrate. A portion of the dielectric layer is removed by etching to form a contact window, exposing the source region, the drain region, or another conductive material region. A first diffusion barrier layer is formed at the bottom and on the sidewalls of the contact window, and on the top surface of the dielectric layer, overhanging the contact window. A photoresist layer is coated over the substrate filling up the contact window and covering the surface of first diffusion barrier layer. An isotropic etching process is performed to etch away portions of the photoresist layer and the first diffusion barrier layer, exposing the surface of dielectric layer, and leaving the height of the aforementioned layers inside the contact window below the top surface of the dielectric layer. The remaining photoresist layer inside the contact window is removed. A second diffusion barrier layer is formed on the exposed upper sidewalls of the contact window, extending to cover the top surface of the dielectric layer as well. A layer of conductive material filling up the contact window then forms the electrical plug.

REFERENCES:
patent: 4822753 (1989-04-01), Pintchowski
patent: 4961822 (1990-10-01), Liao
patent: 5633189 (1997-05-01), Yen

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