Method of fabricating a vertical parallel cell capacitor having

Details Method of fabricating a vertical parallel cell capacitor having Method of fabricating a vertical parallel cell capacitor having

1992-01-24

1992-09-22

Griffin, Donald A.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

437 52, 357 236, 365149, H01G 406, H01L 2170, G11C 700

Patent

active

051502763

ABSTRACT:
The invention is a product and method for forming same comprising a storage contact capacitor of a dynamic random access memory (DRAM) device wherein at least two annular rings and a vertical fin of silicon are fabricated in a self-aligned opening parallel to and in contact with the contact area of the substrate. The rings and fin comprise the storage node of the capacitor, and the fin is substantially centered in the rings. The fin is fabricated by forming silicon in a channel remaining after alternating layers of silicon and oxide are deposited in the opening. The final deposition of oxide is subjected to a spacer etch thereby retaining the final oxide only on sidewalls of the channel. The final oxide then functions as a masking pattern for extending the channel by subjecting the alternating layers to subsequent etches. The silicon fin contacts all of the silicon rings thereby providing electrical communication between the fin and the rings. Once the fin is formed the oxide is exposed, and at least portions of the oxide are etched. A dielectric layer is deposited to overlie the fins and a cell polycrystalline silicon layer is deposited to overlie the dielectric and complete the capacitor fabrication.

REFERENCES:
patent: 4686000 (1987-08-01), Heath
patent: 4849854 (1989-07-01), Eguchi
patent: 4951175 (1990-08-01), Kurosawa et al.
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5081559 (1992-01-01), Fazan et al.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M Drams" pp. 592-595, 1988, by T. Ema et al.

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