Method of fabricating a twin tub CMOS device

Details Method of fabricating a twin tub CMOS device Method of fabricating a twin tub CMOS device

1986-11-26

1987-11-17

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 63, H01L 21425

Patent

active

047074558

ABSTRACT:
A method of fabricating a semiconductor device having a symmetric and complementary P-well and N-well. The novel method involves the introduction of a first dopant type into a semiconductor substrate directly through those regions of an oxide layer and a nitride layer which do not underlie a first mask layer. The first mask layer is removed and a second mask layer is formed. A complementary dopant type is then introduced into the semiconductor substrate directly through those regions of the oxide layer and nitride layer which do not underlie the second mask layer. The second mask layer is removed and the dopant ions are simultaneously subjected to thermal drive in to thereby form adjacent wells of opposite dopant type in the semiconductor substrate.

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