Method of fabricating a transistor structure

Details Method of fabricating a transistor structure Method of fabricating a transistor structure

2006-05-17

2008-08-19

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S300000, C438S589000, C438S700000, C257SE21308, C257SE21431

Reexamination Certificate

active

07413961

ABSTRACT:
The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.

REFERENCES:
patent: 6797556 (2004-09-01), Murthy et al.
patent: 6867428 (2005-03-01), Besser et al.
patent: 6881635 (2005-04-01), Chidambarrao et al.

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