Method of fabricating a thin film transistor

Details Method of fabricating a thin film transistor Method of fabricating a thin film transistor

1994-04-26

1995-04-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 21, 437162, 437913, 437915, H01L 21265

Patent

active

054037611

ABSTRACT:
This invention relates to the Thin Film Transistor having the self-aligned diffused source/drain regions for improving the ratio of on to off current and the method of fabricating the same. The method of making TFT comprising the steps of forming a gate electrode around a central portion of a substrate, forming a gate insulating layer over the substrate and covering the gate electrode, forming a semiconductor layer on the gate insulating layer, forming sidewall spacers on stepped potions of the first semiconductor layer near both sides of the gate electrode, forming a doped semiconductor layer over the whole surface of the substrate, patterning the second semiconductor layer to form one of the patterned second semiconductor layers formed over the first semiconductor layer and apart from the one sidewall spacer near one side of the gate electrode, and the other formed over the first semiconductor layer and the other sidewall spacer near the other side of the gate electrode, and diffusing the impurity in the second semiconductor layer through the anneal process to form highly doped impurity regions in the underlying first semiconductor layer.

REFERENCES:
patent: 4628589 (1986-12-01), Sundaresan
patent: 4656731 (1987-04-01), Larn et al.
patent: 5198379 (1993-03-01), Adam
patent: 5262655 (1993-11-01), Ashida
patent: 5300446 (1994-04-01), Fujioka
Paper entitled "16Mbit SRAM Cell Technologies for 2.0V Operation" by H. Ohkubo, et al., published 1991 in IEDM, pp. 481-484.

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