Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-08-11
2002-10-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S154000, C438S143000, C438S150000, C438S471000, C438S473000
Reexamination Certificate
active
06468872
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 1999-33057, filed on Aug. 12, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor (hereinafter “TFT”), and more particularly, to a method of fabricating TFTs which are used as switching devices in a liquid crystal display (hereinafter “LCD”).
2. Discussion of the Related Art
An active layer of a TFT is formed of a semiconductor substance, having impurity-doped source and drain regions and an undoped channel region. A portion of the impurities of the source and drain regions are concentrated on the channel region by a signal applied to a gate electrode, thereby generating a path through which carriers migrate.
Impurity doping means that impurities, such as electric charges or molecules possessing energy, are implanted or injected into a semiconductor layer. The resulting layer is referred to as a “doped layer”. Impurities, having been accelerated to have some kinetic energy 1 KV to multi MV, are directed to the surface of a semiconductor. The impurities enter into the crystals of the semiconductor, transferring the kinetic energy to the impacted crystal lattices. The impurities stop within the crystals at an averaged depth, called a projected range. The projected range in a given semiconductor may vary 100 Å to about 1 &mgr;m according to the impurity species and the projected energy.
As shown in
FIG. 1
, impurities are distributed symmetrically, with the distribution centering around the projected range Rp (hereinafter “RP”). The distribution of the injected impurities is Gaussian. As shown in
FIG. 1
, &Dgr;RP designates a distribution deviation. RP and &Dgr;RP are proportional to the impurity accelerating voltage.
FIG. 2A
to
FIG. 2D
illustrate cross-sectional views of fabricating a coplanar CMOS TFT according to a related art.
Referring to
FIG. 2A
, areas where an n-type TFT and a p-type TFT will be formed are defined on a substrate
200
. Semiconductor active layers
21
-
1
and
21
-
2
are formed on the respective areas of the substrate
200
. Then, gate insulating layers
22
-
1
and
22
-
2
and gate electrodes
23
-
1
and
23
-
2
are formed on the semiconductor layers
21
-
1
and
21
-
2
, respectively.
Referring to
FIG. 2B
, a first doping-blocking layer DB
1
covering the n-type TFT area is formed. A source region
21
S and a drain region
21
D doped with p-type impurities are formed in the semiconductor layer
21
-
1
of the p-type TFT, thereby defining a channel region
21
C. Channel region
21
C remains undoped. The first doping-blocking layer DB
1
is removed.
Referring to
FIG. 2C
, after the first doping-blocking layer DB
1
has been removed, a second doping-blocking layer DB
2
covering the p-type TFT area is formed. Then, a source region
21
′S and a drain region
21
′D doped with n-type impurities are formed in the other semiconductor layer
21
-
2
of the n-type TFT, thereby defining a channel region
21
′C.
Referring to
FIG. 2D
, the second doping-blocking layer DB
2
covering the p-type TFT area is removed. After an insulating layer
24
covering an entire top surface of the substrate
200
has been formed, contact holes exposing the source and drain regions
21
S and
21
D of the p-type TFT and the source and drain regions
21
′S and
21
′D of the n-type TFT are formed. Then, a CMOS TFT constructed with p- and n-type TFTs complementary to each other is fabricated by forming wires
25
-
1
,
25
-
2
, and
25
-
3
connecting the exposed source and drain regions
21
S and
21
D of the p-type TFT to the exposed source and drain regions
21
′S and
21
′D of an n-type TFT, respectively.
A disadvantage of the related art is the required use of the two doping-blocking layers, to dope p- and n-type TFTs with proper impurities respectively, as shown in
FIGS. 2B and 2C
. Therefore, two masks must be prepared to pattern the two doping-blocking layers, resulting in a complicated process and reducing its product yield.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a thin film transistor (“TFT”) that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a simplified method of fabricating a CMOS TFT by counter-doping using a single impurity doping mask.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of preparing a first conductive type TFT including a first semiconductor layer and a first gate electrode and a second conductive type TFT including a second semiconductor layer and a second gate electrode on a substrate; doping the first and second semiconductor layers with a first conductive type impurity using the first and second gate electrodes as masks; forming a doping mask covering the first conductive type TFT; counter-doping the second semiconductor layer with a second conductive type impurity using the doping mask and the second gate electrode as masks, and a step of forming CMOS TFT by connecting electrically and complementarily the first conductive type TFT to the second conductive type TFT.
Preferably, the first and second conductive types are p and n respectively, a dose of the second doping step is heavier than that of the first doping step, and accelerating voltage of the second doping step is higher than that of the first doping step.
Preferably, the first and second conductive types are n and p respectively and wherein a dose of the second doping step is heavier than that of the first doping step, and accelerating voltage of the second doping step is substantially the same as that of the first doping step.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5591988 (1997-01-01), Arai et al.
patent: 5712495 (1998-01-01), Suzawa
patent: 5904509 (1999-05-01), Zhang et al.
patent: 6087648 (2000-07-01), Zhang et al.
patent: 6133620 (2000-10-01), Uochi
patent: 6204520 (2001-03-01), Ha et al.
patent: 6251712 (2001-06-01), Tanaka et al.
patent: 6337232 (2002-01-01), Kusumoto et al.
L.G. Philips LCD Co., Ltd
McKenna Long & Aldridge LLP
LandOfFree
Method of fabricating a thin film transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a thin film transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a thin film transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2995487