Fishing – trapping – and vermin destroying
Patent
1995-04-04
1996-08-13
Tsai, H. Jey
Fishing, trapping, and vermin destroying
437 40, 437 41, H01L 21265
Patent
active
055455794
ABSTRACT:
A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths, lightly doped source/drain, and shallow junction depths was achieved. The method for fabricating the FET includes a doped pad oxide layer that functions as both an etch stop layer and a diffusion source for the lightly doped drain. The doped pad oxide prevents the substrate from being etched when a channel opening for the gate electrode is etched in a source/drain polysilicon layer. The sub-quarter micrometer channel length was achieved by reducing the channel opening by sidewall spacer techniques. The shallow source/drain junctions out diffused from the polysilicon are about 0.10 to 0.15 um depth, and the lightly doped source/drain junctions are about 0.05 to 0.08 um depth.
REFERENCES:
patent: 4939100 (1990-07-01), Jeuch et al.
patent: 5071780 (1991-12-01), Tsai
patent: 5141891 (1992-08-01), Arima et al.
patent: 5196357 (1993-03-01), Boardman et al.
patent: 5272100 (1993-12-01), Satoh et al.
patent: 5494838 (1996-02-01), Chang et al.
"A Sub-0.1 .mu.m Grooved Gate MOSFET with High Immunity to Short-Channel Effects", by J. Tanaka et al, IEDM Proceedings of the IEEE, 1993, pp. 537-540.
Hsu Charles C.-H.
Liang Mong-Song
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tsai H. Jey
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