Method of fabricating a stacked capacitor for a DRAM cell by pla

Details Method of fabricating a stacked capacitor for a DRAM cell by pla Method of fabricating a stacked capacitor for a DRAM cell by pla

1996-12-13

1998-02-24

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 28242

Patent

active

057211523

ABSTRACT:
A DRAM memory capacitor is formed by depositing a layer of polysilicon on FOX and device areas. Form gate structures and S/D structures by etching through the oxide layer, so openings extend over a portion of the polysilicon layer of the gate structure and the FOX areas. Capacitor plates are formed next. Deposit a first plate into electrical and mechanical contact with one of the S/D structures and dope the first capacitor plate to a high level. Deposit a second plate doped to a low level, a third plate doped to a high level, and a fourth plate doped to a low level. Pattern the plates by etching so the remaining portions lie over planned capacitor areas, with the remainder removed by selective isotropic etching away of portions of the plates doped to a high level to provide fins by removal thereof from between plates doped to a low level. Remove by selective isotropic etching portions of the first plate and the third plate to create an undercut of the second and fourth plates to create fins of the second and fourth plates.

REFERENCES:
patent: 5286668 (1994-02-01), Chou
patent: 5374577 (1994-12-01), Tuan
patent: 5385859 (1995-01-01), Enomoto
patent: 5525534 (1996-06-01), Ikemasu et al.
patent: 5622882 (1997-04-01), Yee
patent: 5637523 (1997-06-01), Fazan et al.
T. Ema, et al., "3D Stacked Capacitor--Cell for 16M DRAMs," IEDM pp. 592-595 (1988).

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