Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from liquid or supercritical state – Having pulling during growth
Reexamination Certificate
2001-01-17
2003-02-11
Hiteshew, Felisa (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth from liquid or supercritical state
Having pulling during growth
C117S020000
Reexamination Certificate
active
06517632
ABSTRACT:
BACKGROUND TECHNIQUE
1. Technical Field to which the Invention Belongs
The present invention relates to method of fabricating a silicon single crystal ingot and method of fabricating a silicon wafer, and particularly to a method of fabricating the silicon single crystal ingot by which a yield of a semiconductor device can be increased. Further, particularly the present invention relates to a method of fabricating the silicon wafer by which a crystal defect of a surface layer is decreased, and the BMD density inside the wafer is increased.
2. Description of the Related Art
The silicon wafer used for the semiconductor device is produced in such a manner that the single crystal ingot pulled up from a polycrystalline silicon by the CZ method is sliced.
The CZ method is a method by which polycrystalline silicon as a raw material supplied into a quartz crucible is heated and fused, and a tip of a seed crystal is brought into contact with the silicon fused liquid, and after being got intimate with it, the silicon single crystal ingot is brought up and pulled up.
In order to conduct gettering the impurity such as heavy metals existing on the surface of the crystal of the silicon wafer in thus produced silicon wafer, the IG method (Intrinsic Gettering)using oxygen precipitate(BMD) is used.
Recently, the densification of the semiconductor device is advanced, and therewith, the decrease of oxygen is required also for the silicon single crystal ingot. On the one hand, the oxygen deposit in the silicon wafer produced from this silicon single crystal ingot is essential to the IG method, however, the oxygen deposit is decreased due to the decrease of the oxygen.
Accordingly, a method by which nitrogen is doped in the polycrystalline silicon fused liquid, and the deposit of oxygen is promoted in the crystal of the silicon wafer, is conducted, however, the nitrogen doping generates a ring-like oxide induction lamination layer defect called OSF ring, when the thus produced silicon wafer is subjected to the thermal oxidization processing, and the width of the OSF ring area is increased. Further, inside the OSF ring, the area in which the density of the oxygen deposit is greatly low exists, and in a portion in which the density of the oxygen deposit is greatly low and uneven, the gettering ability is lower than the other portion, and the predetermined gettering ability can not be obtained, and the oxide film with stand voltage is lowered, and the yield of the semiconductor device is lowered.
Further, the electric characteristic, especially, the aging dielectric breakdown characteristic of the oxide film is lowered, and as a factor to lower the yield of the semiconductor device, there is an etch pit generated after the etching of the silicon wafer.
That is, in the semiconductor device production process, as a cause to lower the yield, the existence of COP (Crystal Originated Particle) is listed (refer to FIG.
5
), and this COP is one of the crystal defects introduced at the time of the crystal growing, and is a cavity type defect of the regular octahedron. This COP forms a pit on the surface of the silicon wafer when the silicon wafer after the specular polishing is etched by a mixed liquid of ammonium and hydrogen peroxide (etch pit, refer to FIG.
7
), and deteriorates the aging dielectric breakdown characteristic of the oxide film of the silicon wafer, and further, is a factor of the lowering of the yield in the semiconductor device production process.
As a method to suppress the etch pit density, in order to suppress the introduction of the COP in the single crystal growing process which is the cause of the etch pit generation, the lowering of the pulling up speed of the single crystal is conducted. However, in this single crystal pulling up method, the productivity is lowered and the practicability is poor.
Further, as another method, in JP-A-3-193698, a method by which oxygen, nitrogen, and D defect are contained in the silicon wafer sliced from the silicon ingot produced by FZ method, and when it is heat-treated, even when an amount of oxygen is comparatively small and even under the existence of nitrogen, the heavy metal can be gettered, is disclosed.
However, this disclosed method is the FZ method, and there is no countermeasure for the defect existing in the surface layer (depth of several &mgr;m from the surface).
Further, in JP-A-5-294780, a method by which nitrogen is doped in the polycrystalline silicon fused liquid, is disclosed, and, in the nitrogen doping, it is disclosed that Secco-etch pit is not above 300 pits/cm
2
, however, in the same way as in the above, there is no countermeasure for the defect existing in the surface layer which influences the yield of the semiconductor device.
Further, in JP-A-11-195565, a method to produce the silicon wafer in which nitrogen is doped in the polycrystalline silicon; the single crystal is pulled up at low speed by using the Czochralski method; the nitrogen density is controlled; and the OSF ring is generated in the inside from the outer periphery of the crystal, or vanished at the central portion, is disclosed, however, the method is a method in which the single crystal is pulled up at the low speed, and the productivity is low and the practicability is poor.
Further, in order to reduce COP which is a cause of the etch pit, it is also effective to anneal the silicon wafer in the hydrogen atmosphere at the high temperature, and many methods are proposed.
For example, as disclosed in JP-A-11-186277, it is a method in which the pulling up speed of single crystal in the CZ method is increased, and the silicon wafer in which the COP size is 60-130 nm, is heat-treated in the reduction atmosphere. However, the hydrogen annealing is effective as a method to vanish the COP existing on the silicon wafer surface, and the COP decreasing effect of the surface is recognized to be conspicuous, however, a considerable numbers of COPs remain on the surface, and in the surface layer of about 5 &mgr;m depth from the surface which largely influences on the yield of the semiconductor device, the COP remains. Further, only by the size reduction of the COP by the increase of the pulling up speed (higher than 0.6 mm/min) disclosed in the official specification, the vanishing of the surface layer COP can not also be attained.
Further, in JP-A-11-135514, a method by which the silicon wafer having the COP density of not larger than 0.16 pits/cm
2
, is produced by the heat treatment in the mixture atmosphere of hydrogen and argon, is disclosed, however, in order to vanish the COP existing in the surface layer of about 5 &mgr;m depth from the surface by the hydrogen annealing, it is necessary to make the silicon single crystal controlled in the shape in which the COP before the annealing is easily vanished. However, there is no consideration about which shape silicon single crystal is preferable.
Further, as a factor by which the oxide film withstand voltage or the aging dielectric breakdown characteristic of the oxide film is decreased, and the yield of the semiconductor device is decreased, other than the COP (Crystal Originated Particle) existing as the Grown-in defect in the silicon single crystal ingot pulled up by the CZ method, LSTD (Laser Scattering tomography defect), and FPD (Flow Pattern Defect) are considered.
That is, this COP is, as described above, considered as an aggregate of holes (transition loop or regular octahedron void (void defect)), and when the silicon wafer after the specular polishing is etched by the mixed liquid of ammonium and hydrogen peroxide, this COP forms the pit on the surface of the silicon wafer (etch pit), and deteriorates the oxide film withstand voltage or the aging dielectric breakdown characteristic of the oxide film of the silicon wafer, and becomes a factor of the decreasing of yield in the semiconductor device production process.
Further, as the result of the advance of the temperature lowering of the process of the semiconductor device, the COP of 0.1-0.2 &mgr;m level is hardly vanished in the process, and deteriorate
Hirano Yumiko
Ikeuchi Kouki
Ishikawa Takashi
Kobayashi Akihiko
Kubota Osamu
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