Method of fabricating a shallow-trench isolation structure in an

Details Method of fabricating a shallow-trench isolation structure in an Method of fabricating a shallow-trench isolation structure in an

1998-12-07

1999-12-28

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438438, 438435, 148DIG50, H01L 2176

Patent

active

060081082

ABSTRACT:
A semiconductor fabrication method is provided for the fabrication of a shallow-trench isolation (STI) structure in integrated circuit. Conventionally, the insulating plug of the STI structure would be undesirably formed with microscratches in its top surface resulting from chemical-mechanical polishing (CMP) process, thus causing an undesired bridging effect thereacross when conductive layers are subsequently formed. This method can help solve this problem by forming a mending dielectric layer over the insulating plug of the STI structure to mend these microscratches. Since the mending dielectric layer is in a flowable state when it is being coated over the wafer, it can fill up all the microscratches in the top surface of the insulating plug, thereby mending the microscratches to prevent the bridging effect across the insulating plug that would other-wise occur in the case of the prior art. This method can thus help the resulting IC device to be more reliable in operation and also can help increase the yield rate of the wafer fabrication.

REFERENCES:
patent: 5189501 (1993-02-01), Kawamura et al.
patent: 5435888 (1995-07-01), Kalnitsky et al.
patent: 5795811 (1998-08-01), Kim et al.
patent: 5872043 (1999-02-01), Chen

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