Method of fabricating a shallow trench isolation structure

Details Method of fabricating a shallow trench isolation structure Method of fabricating a shallow trench isolation structure

2002-10-09

2004-05-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S243000, C438S244000, C438S430000, C438S435000, C438S524000, C438S745000, C438S749000, C438S751000, C438S756000

Reexamination Certificate

active

06737334

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for fabricating a shallow trench isolation (STI) structure.
2. Description of the Related Art
Advances in the production of integrated circuits have led to an increase in the level of integration and the miniaturization of semiconductor devices. As the level of integration increases, both the dimensions of each device and size of the isolating structures between devices are reduced. Consequently, device isolation structures are increasingly harder to form. A device isolation structure such as a field oxide layer formed by local oxidation (LOCOS) is no longer suitable for small dimensional devices due to the intensification of bird's beak encroachment. Therefore, the shallow trench isolation (STI) method has been developed for highly integrated circuits, and, in particular, sub-half micron integrated circuits.
A typical process for shallow trench isolation fabrication generally includes the following steps. First, a shallow trench is formed in a semiconductor substrate by selective etching. Second, an insulating layer is deposited on the entire surface of the semiconductor substrate to fill the trench. The insulating layer is typically formed of silicon dioxide by chemical vapor deposition (CVD), such as atmospheric pressure chemical vapor deposition (APCVD), sub-atmospheric pressure chemical vapor deposition (SACVD) or high density plasma CVD (HDPCVD). Finally, CMP is used to planarize the insulating layer, thus the insulating layer remaining in the trench serves as a STI region.
Because of the increasing complexity of electronic devices, the dimensions of semiconductor devices are shrinking, while the width of STI regions is decreasing to 0.11 &mgr;m or less, and the aspect ratio of STI regions is increasing beyond 3. Even if a HDPCVD with good filling capability is employed, voids or seams still exist in the STI regions and one-step coverage is hard to achieve. When conductive materials are deposited in subsequent processes, these defects cause short circuits between devices, thus reducing the lifetime of the device.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to solve the above-mentioned problems and to provide a method of fabricating a high aspect ratio shallow trench isolation structure.
The present invention discloses a method of fabricating a shallow trench isolation structure in a semiconductor substrate, comprising the following steps. A trench is formed on the semiconductor substrate. A liner oxide is formed on the bottom and sidewall of the trench. A liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H
2
SO
4
=0.3~0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition (HDPCVD).
In a preferred embodiment, the aspect ratio of the trench is greater than 3. The second oxide layer, i.e. an HDP oxide layer, can be annealed to increase the density thereof after the second oxide layer is deposited and the second oxide layer can be subsequently planarized by chemical mechanical polishing (CMP) to form a well-filled shallow trench isolation structure.
In another preferred embodiment, the trench can be formed by reactive ion etching (RIE). The liner oxide cab be formed by thermal oxidation and the liner nitride can be formed by low pressure CVD (LPCVD).
The preferred thickness of the first oxide layer in the trench is about 2000-5000 Å. The preferred recipe of the spray etching solution is HF:H
2
SO
4
=1:2 and the spray etching is performed for 20-30 seconds. The preferred thickness of the second oxide layer in the trench is about 3000-6000 Å. The first and second oxide layer can be silane based HDP oxide.


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