Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Patent
1998-06-16
2000-07-25
Nelms, David
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
438400, 438296, 438401, 438424, 438435, 438437, H01L 2176
Patent
active
060936185
ABSTRACT:
A method of fabricating a shallow trench isolation structure includes defining a shallow trench isolation region on a substrate covered by a first oxide layer and a mask layer. Then, covering the inner surface of the shallow trench with a silicon nitride layer. After a thermal treatment, two oxide layers are formed at the two sides of the silicon nitride layer, respectively. Then, another oxide layer is formed to fill the shallow trench. Next, a planarization process is performed until the mask layer is exposed. The mask layer and the first oxide layer and the oxide layer higher than the substrate are removed.
REFERENCES:
patent: 5950093 (1999-09-01), Wei
patent: 5963819 (1999-10-01), Lan
patent: 5970363 (1999-10-01), Kepler et al.
patent: 5981353 (1999-11-01), Tsai
Chen Chih-Rong
Hsieh Yong-Fen
Tsou Yunn-Ming
Dang Phuc T.
Nelms David
United Microelectronics Corp.
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