Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-10-26
2001-11-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000, C438S223000, C438S224000, C438S296000, C438S433000, C438S434000
Reexamination Certificate
active
06316330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a semiconductor device. More particularly, this invention uses a method of fabricating a metal oxide semiconductor (MOS) with a gate formed in an active region of a substrate isolated by an isolation structure filled with doped insulation material.
2. Description of the Related Art
Shallow trench isolation is currently a wide applied isolation structure in integrated circuit. The demand of fabricating an integrated circuit with a high integration has made the elements, including the isolation structures and devices such as metal-oxide semiconductors (MOS), formed on a semiconductor substrate become smaller and smaller.
In the conventional method for fabricating a shallow trench isolation, a pad oxide is formed on a substrate prior to forming a trench followed by filling the trench with an undoped insulation material. The pad oxide layer is then removed after the trench is filled, and a gate oxide layer is formed on the substrate. It is very often that the substrate is damaged during the removal of the pad oxide layer. Or the pad oxide layer can be removed improperly to cause a poor integrity of the gate oxide layer formed subsequently. This seriously affects the device reliability.
In addition, by filling the trench with an undoped insulation material, a great difference in thermal expansion coefficient and Young's modulus is induced between the substrate and the undoped insulation material filled within the trench. As a consequence, the substrate is experience a stress during any subsequent thermal process to cause physical defects such as the deformation of the undoped insulation material . A junction leakage and a sub-threshold leakage are thus very likely to be induced.
Other problems due to the size reduction of semiconductor devices include the well-known “short channel effect”. A variety of methods have been proposed to resolve this problem. However, the shrinkage of a MOS device consequently has a reduced gate length and it is thus inevitable to cause a punch through between a source region and a drain region.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a shallow trench isolation as well as a method of fabricating a metal-oxide semiconductor buried in a substrate. In the method of fabricating the shallow trench isolation, a substrate is provided. A gate oxide layer, a first wiring layer and a mask layer are formed on the substrate sequentially. The mask layer is patterned to expose a portion of the first wiring layer under which a trench is to be formed. The exposed first wiring layer, the underlying gate oxide layer and the substrate are etched to form the trench. The trench is filled with a doped silicon oxide layer. The mask layer is then removed, followed by the formation of a second wiring line and a photolithography and etching process on the first and the second wiring layers. Optionally, a well region can be formed prior to the formation of the gate oxide layer.
In the method of fabricating a metal-oxide semiconductor, a substrate having an active region isolated by a shallow trench isolation filled with doped silicon oxide is provided. The substrate may also include a well region formed prior to the formation of the shallow trench isolation. A trench is formed by removing a portion of the substrate in the active region. A spacer and a gate oxide are formed respectively on a sidewall and a bottom surface of the trench. The trench is the filled with a conductive layer to form a gate. Using the gate, the spacer and the shallow trench isolation as a mask, a source/drain region is formed between the shallow trench isolation and the gate. A salicide layer is formed on the source/drain region and the gate.
The method of fabricating a shallow trench isolation with a gate oxide layer formed prior to forming a trench eliminating the problems of damaging the substrate for forming a pad oxide layer followed by a removal step. In addition, an integrity of the gate oxide layer can be obtained since no etch is performed on the required portion of the gate oxide layer. Moreover, the gate oxide layer is covered and thus protected by the lower wiring layer from being damaged according to any external contamination or force. The option of forming a well region prior to the formation of the gate oxide further prevents the gate oxide from being damaged by ion implantation. Furthermore, it is known that while filling the trench with an insulation material, a stress is incurred during a subsequent thermal process due to a large difference in thermal expansion coefficient and Young's modulus between the substrate and the semiconductor. In addition to the deformation of the filling material and other physical defects, a junction leakage and a sub-threshold leakage may also occur. For dense pattern areas and high packing density memory devices, these even cause the devices. Substituting the undoped silicon oxide used in the conventional method with a doped silicon oxide, the thermal expansion coefficient and Young's modulus can be adjusted as specifically required. The stress can thus be suppressed, and consequently, the junction leakage and the sub-threshold leakage which cause devices failure can be eliminated.
The invention also provides a method of fabricating a buried-in metal-oxide semiconductor. A gate is formed buried in the substrate with a spacer or a gate oxide layer isolating the gate from both the source region and the drain region. In this manner, the channel length can be adjusted as required by controlling the depth of the gate, so that the short channel effect can be resolved. Furthermore, the source/drain regions as well as a salicide layer can be formed with a self-aligned manner, so that the reliability is enhanced.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
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Chen Coming
Lur Water
Yang Gwo-Shii
Yew Tri-Rung
Gurley Lynne A.
Niebling John F.
United Microelectronics Corp.
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