Method of fabricating a semiconductor mesa device

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal

Reexamination Certificate

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C438S031000

Reexamination Certificate

active

06399403

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices, and in particular to forming such devices which include a mesa geometry.
BACKGROUND OF THE INVENTION
Typical semiconductor optoelectronics devices, such as lasers, involve forming a mesa in order to define the lateral dimensions of the device. For example, a standard fabrication sequence includes epitaxially forming several semiconductor layers on a semiconductor wafer, and then selectively etching the layers to form plateaus or mesas, thereby defining the individual devices.
One particular device which is receiving increasing attention is the Expanded Beam Laser (XBL). This type of laser is fabricated by removal of part of the active region in such a way as to direct the light beam toward an underlying waveguide layer. The waveguide layer is designed to allow the light to expand, or diverge, as is propagates. The fabrication of such devices typically includes a diagonal lateral taper etch of the epitaxial layers across the axial mesa direction prior to mesa etching in order to couple the light beam into the waveguide. (See, e.g., U.S. Patent Application of Johnson 6-19-8-1-3, Serial No. 09/228218, filed Jan. 11, 1999 and assigned to Lucent.) Upon mesa etching, undesirable morphology can be created at the intersection of the mesa and lateral taper etch regions. This results in unequal amounts of residual material on either side of the mesa stripe, producing a bulge in the mesa. This mesa bulge can cause significant reliability problems.
It is, therefore, desirable to provide a process for forming mesa devices which reduces or eliminates the formation of mesa bulge.
SUMMARY OF THE INVENTION
The invention is a method of fabricating semiconductor devices including the steps of selectively etching at least a first semiconductor layer on a semiconductor wafer so as to perform a lateral taper etch in said layer, forming a second layer over the etched region so as to planarize the etched area, and subsequently performing a second etch in a portion of the etched area so as to form a mesa geometry.


REFERENCES:
patent: 5771321 (1998-06-01), Stern
patent: 5862168 (1999-01-01), Schilling et al.
patent: 5888844 (1999-03-01), Bestwick et al.
patent: 6052397 (2000-04-01), Jeon et al.
patent: 6162655 (2000-12-01), Jhonson et al.
patent: 6180429 (2001-01-01), Anselm et al.
patent: 6194240 (2001-02-01), Chiu et al.

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