Method of fabricating a semiconductor memory device

Details Method of fabricating a semiconductor memory device Method of fabricating a semiconductor memory device

1992-06-09

1993-09-28

Kunemund, Robert

Fishing, trapping, and vermin destroying

437 52, 437 60, 437919, H01L 2170, H01L 21265

Patent

active

052486281

ABSTRACT:
A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

REFERENCES:
patent: 4979013 (1990-12-01), Furutani et al.
patent: 5091761 (1992-02-01), Haraiwa et al.
patent: 5101251 (1992-03-01), Wakamiya et al.
patent: 5120674 (1992-06-01), Chris et al.
patent: 5140389 (1992-08-01), Kimura et al.
"Dynamic Semiconductor RAM Structures," p. 12, which refers to IBM Technical Bulletin, vol. 15, No. 12, pp. 3585-3586, May 1, 1973.

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