Fishing – trapping – and vermin destroying
Patent
1988-11-15
1990-02-06
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 47, 437 27, 437918, 357 51, H01L 21265
Patent
active
048988375
ABSTRACT:
A method of fabricating a semiconductor integrated circuit comprises the steps of: forming buried layers in predetermined regions of a semiconductor substrate; forming an epitaxial layer covering the substrate and the buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; selectively implanting ions to form a base region of a vertical bipolar transistor in a surface layer of one island and simultaneously to form a resistor region in a surface layer of another island; and selectively diffusing impurities into a surface layer of the base region, to form an emitter region of the vertical bipolar transistor.
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Fujunuma Chikao
Hayasaka Katsuhiro
Itoh Nobuo
Kubota Tetsuya
Sekikawa Nobuyuki
Hearn Brian E.
Nguyen Tuan
Sanyo Electric Co,. Ltd.
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