Method of fabricating a semiconductor embedded dynamic random-ac

Details Method of fabricating a semiconductor embedded dynamic random-ac Method of fabricating a semiconductor embedded dynamic random-ac

1998-07-10

2000-08-22

Nelms, David

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438300, H01L 2120

Patent

active

061071544

ABSTRACT:
A semiconductor fabrication method is provided for the fabrication of an embedded DRAM (dynamic random-access memory) device. This method is also suitable for use in the fabrication of an embedded DRAM device with dual-gate CMOS (complementary metal-oxide semiconductor) structure. The method is characterized in that the titanium silicide layers in the embedded DRAM device are formed by first performing an SEG (selective epitaxial growth) process so as to form a plurality of amorphous silicon layers over the polysilicon gates and the source/drain regions of the various FET (field effect transistor) elements in the embedded DRAM device, and then performing a self-aligning silicide process on these amorphous silicon layers. This allows the titanium silicide layers to be isolated by the source/drain regions from the substrate. As a benefit of this, formation of the titanium silicide layers does not deplete part of the silicon atoms in the substrate as in the prior art, thus preventing a further thinning of the shallow junction that would cause leakage current in the DRAM device.Because the silicide layers of an embedded DRAM device with dual-gate CMOS structure are formed after the activation of the impurities in the source/drain regions, an embedded DRAM with a dual gate CMOS structure can prevent the occurrence of an inter-diffusion effect between the N-type polysilicon layer and the P-type polysilicon layer in the dual-gate CMOS structure.

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