Method of fabricating a semiconductor device with...

Details Method of fabricating a semiconductor device with... Method of fabricating a semiconductor device with...

2002-02-11

2003-05-06

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having multiple emitter or collector structure

C438S138000

Reexamination Certificate

active

06559023

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device and in particular, to a method for manufacturing a semiconductor device that constitutes an insulated gate bipolar transistor.
BACKGROUND
Insulated gate bipolar transistors (hereinafter referred to as IGBTs), specifically the devices of planar gate structures as shown in FIG.
30
and FIG.
31
and the devices of trench gate structures as shown in FIG.
32
and
FIG. 33
, are known. A non-punch-through type IGBT as shown in
FIG. 30
or
FIG. 32
comprises a base layer
2
that is composed of an n-type semiconductor substrate made of for example an FZ wafer; a p-type channel diffusion region
3
, an n-type emitter diffusion region
4
, an emitter electrode
5
, a gate-insulating film
6
, a gate electrode
7
, and an insulator film
8
, which are formed on one surface of the substrate; and a p-type collector layer
9
and a collector electrode
10
, which are formed on the reverse surface side of the substrate.
A punch-through type IGBT as shown in FIG.
31
and
FIG. 33
employs a wafer, that is an epitaxial wafer, and comprises a p-type wafer Ii, an n-type semiconductor layer
12
, and another n-type semiconductor layer
13
having the impurity concentration lower than that of the n-type semiconductor layer
12
, the both n-type semiconductor layers being epilaxially grown on the p-type wafer ii. The body of the p-type wafer
11
constitutes a collector layer; the n-type semiconductor layer
12
on the collector layer constitutes a buffer layer; and the n-type semiconductor layer
13
on the buffer layer constitutes a base layer
2
. In the surface region on the side of the base layer
2
of the epitaxial wafer, formed are a p-type channel diffusion region
3
, an n-type emitter diffusion region
4
, an emitter electrode
5
, a gate-insulating film
6
. a gate electrode
7
, and an insulator film
8
. A collector electrode
10
is formed on the surface of the side of the collector layer
11
, which is the reverse side of the epitaxial wafer.
However, the non-punch-through type IGBT mentioned above has a disadvantage of large losses because of the thick base layer
2
, which is required so that the depletion layer in the turn-off operation does not extend beyond the thickness of the base layer
2
. In the punch-through type IGBT that is also mentioned above, the thickness of the base layer
2
is about 120 &mgr;m for an example of a blocking voltage class of 1,200 V. The thickness value is smaller than the thickness of about 180 &mgr;m of the base layer of a non-punch-through type IGBT, which results in a lower losses of the punch-through type IGBT. However, the punch-through type IGBT has a disadvantage of its higher cost of the chip caused by the lower yield of the chip and the higher cost (over twice) of the epitaxial wafer than the FZ wafer.
In view of the foregoing, it would be desirable to provide a method for manufacturing a semiconductor device constituting an IGBT that can be produced with a high yield using an inexpensive wafer and generates little loss.
SUMMARY OF THE INVENTION
The present invention is directed to a method for manufacturing a semiconductor device, the method using a wafer, for example an FZ wafer that is cut from an ingot and polished and cleaned on its surface, the bulk part of the wafer composing a base layer. The method comprises steps of forming a p-type channel diffusion layer, an n-type emitter diffusion layer, an emitter electrode, a gate-insulating film, and a gate electrode in one principal surface region of the wafer. After that, the method further comprises steps of implanting phosphorus ions into a shallow portion of a reverse surface region of the wafer, and subsequently implanting boron ions into a shallower portion of the wafer. Then, the wafer is annealed to form an n-type impurity diffusion layer (hereinafter referred to as a field-stop layer) for stopping an electric field during turn-off and a collector layer, on which a collector electrode is formed.
The thickness of this field-stop layer defined by Xfs−Xj is from 0.5 &mgr;m to 3 &mgr;m, where Xfs is the position at which the impurity concentration in the field-stop layer becomes twice the impurity concentration of the base layer, and Xj is the position of the junction between the field-stop layer and the collector layer.
One reason why the thickness of the field-stop layer, Xfs−Xj, is in the above indicated range is that when forming the field-stop layer by means of ion implantation, the maximum depth is 3 &mgr;m due to the energy limit of the ion implantation available at present. On the other hand, the reason for the lower limit is that a diffusion layer thinner than the above-indicated lower limit is difficult to be formed by ion implantation with precise control.
Advantageously, a contact layer may be formed by implanting boron ions or BF
2
+
ions before forming the collector electrode. The contact layer allows the collector electrode to contact electrically with the collector layer with low resistance.
Advantageously, the boron ions are implanted holding the semiconductor substrate at a temperature lower than the room temperature, for example at 80 K. When the boron ions are implanted at such a low temperature, the activation rate in an annealing operation is higher than the implantation at a temperature not lower than the room temperature, and the activation rate of 15% to 60% can be attained for annealing temperatures between 400° C. to 550° C. This is effective for increasing boron concentration in the collector layer without increasing the amount of ions implanted in the collector layer and without elevating the annealing temperature.
Annealing temperature after the ion implantation is appropriately in the range from 300° C. to 550° C. in the case where the annealing is executed in a diffusion furnace, and in the range from 300° C. to 600° C. in the case where the annealing is conducted by means of rapid thermal annealing. One reason for the upper limit is to prevent the emitter electrode from melting and the contact resistance from raising. Another reason is to suppress the activation rate of phosphorus below 15% so that the boron concentration is kept higher than the phosphorus concentration, while the lower limit is the lowest temperature for activating the implanted phosphorus ions.
When the annealing after the ion implantation is performed by laser annealing, the wavelength of the laser light is preferably in the range from 150 nm to 1,060 nm, and the irradiation energy density is appropriately from 0.5 J/cm
2
to 3 J/cm
2
. The reason for the upper limit of 3 J/cm
2
of irradiated energy density is to suppress surface roughness, center line average height, to not more than 1 &mgr;m so as to restrain leakage current minimum. The lower limit of the irradiation energy density is determined because irradiation with the lower energy density hardly activates the implanted ions.
The annealing after ion implantation may be any combination of two or three of the above-mentioned annealing methods: diffusion furnace annealing, rapid thermal annealing, and laser annealing. This is because the combined annealing brings about higher activation rate of the boron ions.
The center line average height Ra of the ion implanted surface is preferably not larger than 1 &mgr;m. When the Ra is within this limit, leakage current Ir can be less than 1 mA which is the acceptable limit. However, when the Ra exceeds 1 &mgr;m, the leakage current rises to 1 mA or more and thermal runaway becomes liable to occur. The centerline average height is specified in article B0601 of Japanese Industrial Standards.
The filtered center line waviness Wca of the surface implanted with the impurity ions is preferably not larger than 10 &mgr;m. When the filtered center line waviness Wca is within this limit, drop of the blocking voltage is insignificant. However, the Wca exceeds 10 &mgr;m, the blocking voltage falls sharply. The filtered center line waviness is specified in article B061

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