Method of fabricating a semiconductor device using a tri-layer s

Fishing – trapping – and vermin destroying

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437 33, 437147, 437160, 437161, 437162, 357 34, 357 59, 148DIG10, 148DIG11, H01L 2100, H01L 2102, H01L 21265

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049944002

ABSTRACT:
A semiconductor device is made from a body of semiconductor material having a layer of dielectric material and a first layer of conductive material over a main face of the body, the layers each having an opening therein through which an area of the main face of the body of semiconductor material is exposed. A second layer of conductive material is formed over the sides of the opening and the conductor material, whereby the second layer of conductive material is in conductive contact with the first layer of conductive material along the sides of the opening. Material of the second layer of conductive material is removed to a depth such that a portion of the main face of the body of semiconductor material is exposed but a sidewall of conductive material remains along a side of the opening and provides an electrically conductive connection between the first layer of conductive material and the body of the semiconductor material.

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patent: 4847670 (1987-07-01), Monkowski et al.
patent: 4916083 (1990-04-01), Monkowski et al.
Nakamura, T., Self-Aligned-Transistor with Sidewall Base Electrode, IEEE Trans. on Elect. Dev., vol. ED-29, No. 4, 1982, 596-600.
Konaka, S., A 30-ps Si Bipolar IC Using Super Self-Aligned Process Tech., IEEE Trans. on Elect. Dev., vol. ED-33, No. 4, Apr. 1986, pp. 526-531.
Yamaguchi, T., Process and Device Performance of a High-Speed Double Poly-Si Bipolar Tech. Using Bososenic-Poly Process with Coupling-Base Implant, IEEE Trans. on Elec. Dev., vol. 35, No. 8, Aug. 1988, pp. 1247-1256.
Sakai, T., Prospects of SST Technology for High Speed LSI, IEDM 85, 1985, IEEE, pp. 18-21.
Ghandhi, S., VLSI Fabrication Principles, pp. 421-422, 1983, Wiley & Sons.

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