Method of fabricating a semiconductor device having shallow junc

Details Method of fabricating a semiconductor device having shallow junc Method of fabricating a semiconductor device having shallow junc

1994-10-07

1995-12-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 45, 437174, 437907, H01L 2126, H01L 21265, H01L 21306, H01L 21479

Patent

active

054749409

ABSTRACT:
A method of fabricating a semiconductor device comprises: a first annealing process for annealing a semiconductor substrate provided with element isolating regions and gate electrode regions; and a second annealing process for annealing the semiconductor substrate further provided with source-drain regions with a pulse laser beam. The first annealing process is a furnace annealing process of a rapid thermal annealing process. Most preferably, the pulse laser beam may be emitted by a XeF laser which emits a laser beam of 351 nm in wavelength or a XeCl laser which emits a laser beam of 308 nm in wavelength. The first annealing process activates electrically relatively thick conductive layers formed in the element isolating regions and gate electrode regions and forms a silicide layer of a low resistance over the gate electrode regions. The second annealing process forms relatively shallow junctions in the source-drain regions.

REFERENCES:
patent: 4330931 (1982-05-01), Liu
patent: 4406053 (1983-09-01), Takasaki et al.
patent: 4434013 (1984-02-01), Bol
patent: 4443930 (1984-04-01), Hwang et al.
patent: 4468855 (1984-09-01), Sasaki
patent: 4555842 (1985-12-01), Levinstein et al.
patent: 4621411 (1986-11-01), Havemann et al.
patent: 4651408 (1987-03-01), MacElwee et al.
patent: 4682408 (1987-07-01), Takebayashi
patent: 4710477 (1987-12-01), Chen
patent: 4914500 (1990-04-01), Liu et al.
patent: 4956311 (1990-09-01), Liou et al.
patent: 5183780 (1993-02-01), Noguchi et al.
patent: 5190886 (1993-03-01), Asahina
patent: 5272361 (1993-12-01), Yamazaki
patent: 5399506 (1995-03-01), Tsukamoto
patent: 5401666 (1995-03-01), Tsukamoto
1 Stanley Wolf and Richard N. Tauber, Silicon Processing For The VLSI Era 384-388 (1986).

Affiliated with

Also associated with

Rating

Method of fabricating a semiconductor device having shallow junc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a semiconductor device having shallow junc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a semiconductor device having shallow junc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1359391