Fishing – trapping – and vermin destroying
Patent
1996-03-07
1997-11-18
Trinh, Michael
Fishing, trapping, and vermin destroying
437141, 437974, 148DIG12, H01L 2138
Patent
active
056887140
ABSTRACT:
A method is set forth of manufacturing a silicon body (5) having an n-type top layer (1') and an adjoining, more highly doped n-type base layer (2'), by which a first, n-type silicon slice (1) and a second, more highly doped n-type silicon slice (2) are put one on the other and then bonded together by heating. To obtain a low contact resistance between top layer (1') and base layer (2'), a boundary layer having a higher doping than the to player (1') is provided in the top layer (1') adjoining the base layer (2'). According to the invention, the boundary layer is formed by diffusion of an n-type dopant (11, 14) into the first slice (1) from the second slice (2) during heating. The concentration of the n-type dopant (11, 14) is taken to be so high in this case that boron (12) present as an impurity is overdoped, so that undesired pn transitions cannot occur. Measures according to the invention present the advantage that pollution of the first slice (1) is counteracted, while in addition the boundary layer is given a steep concentration profile. Semiconductor devices manufactured in body (5) will as a result have a comparatively high switching speed and a comparatively low forward bias.
REFERENCES:
patent: 3638301 (1972-02-01), Matsuura
patent: 3879230 (1975-04-01), Nakamura et al.
patent: 4638552 (1987-01-01), Shimbo et al.
patent: 4700466 (1987-10-01), Nakagawa et al.
patent: 4703553 (1987-11-01), Mardesich
patent: 4738935 (1988-04-01), Shimbo et al.
patent: 4837177 (1989-06-01), Lesk et al.
patent: 4837186 (1989-06-01), Ohata et al.
patent: 4931408 (1990-06-01), Hshieh
patent: 4935386 (1990-06-01), Nakagawa et al.
Silicon Processing for the VLSI Era; vol. 1; Wolf et al pp. 12, 21-25; 1986 .
De Kock Arie J. R.
Haisma Jan
Van Gorkum Aart A.
Widdershoven Franciscus P.
Trinh Michael
U.S. Philips Corporation
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