Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-02-01
2001-07-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S118000, C438S123000, C438S125000, C257S666000
Reexamination Certificate
active
06258621
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the structure of a semiconductor device, especially to the structure of a plastic packaged semiconductor device and its fabrication method.
In recent years, in plastic packaged semiconductor devices, with an increased size of a pellet (chip), the dimension between the edge of a package and a semiconductor element tends to be increasingly smaller. This is because, although the semiconductor element has become large in size, the size of a package for housing it has been standardized and cannot be made larger. Accordingly, in order to solve such a problem, a plastic packaged semiconductor device of an LOC (Lead On Chip) structure as disclosed in Japanese Patent Kokoku Publication
6
-
105721
has come into use.
The plastic packaged semiconductor device of this LOC (Lead On Chip) structure is structured such that leads are bonded to the surface of a semiconductor element via insulating tapes, gold wire platings applied to the top surfaces of the leads and gold balls on the electrodes of the semiconductor element are connected by means of gold wires, and in addition, they are sealed by a resin material.
However, as a major problem with such conventional plastic packaged semiconductor devices, it sometimes happens, for example, that the function is impaired by a crack produced in the resin material due to the heat during the mounting on a board. If the resin becomes moist, having absorbed moisture while the semiconductor device is kept in the air, the moisture is vaporized due to the heat during the mounting on the board, and the force produced from it may bring about the crack. The insulating tape is particularly apt to absorb moisture, so that it often happens that a crack is produced from the area around the insulating tape. Further, as another problem, since there is the insulating tape, the reduction in the thickness of the semiconductor device is subject to a limitation.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above-mentioned problems. It is therefore an object of the present invention to provide a plastic packaged semiconductor device capable of preventing the generation of a crack and being made thinner, and its fabrication method.
The present invention is characterized in that a chip support is provided besides leads, only the chip support is attached to a semiconductor element and the leads are not fixed to a semiconductor element, and the electrodes of the semiconductor element and the leads are connected.
With this configuration, since there is no particular material between the leads and the surface of the semiconductor element for fixing them, the thickness of the combination of the leads and the semiconductor element can be reduced. The thickness of the whole device can be thereby reduced. In addition, since an insulating tape is employed solely for bonding the semiconductor element to the chip support, the area of the insulating tape to be used is very small. Generation of a crack inherent in the insulating tape can be thereby prevented, and the quality can be improved.
REFERENCES:
patent: 3887998 (1975-06-01), Hartleroad et al.
patent: 4490903 (1985-01-01), Agatahama
patent: 4697203 (1987-09-01), Sakai et al.
patent: 4935803 (1990-06-01), Kalfus et al.
patent: 5068712 (1991-11-01), Murakami et al.
patent: 5146312 (1992-09-01), Lim
patent: 5307978 (1994-05-01), Ricketson et al.
patent: 5519251 (1996-05-01), Sato et al.
patent: 5776802 (1998-07-01), Ochi et al.
patent: 6068174 (2000-05-01), Ball et al.
patent: 6097083 (2000-08-01), Ohuchi et al.
patent: 6143589 (2000-11-01), Corisis et al.
patent: 0 657 931 A1 (1994-12-01), None
patent: 6 129 673 0 (1986-12-01), None
patent: 0 113 495 8 (1989-05-01), None
patent: 0 305 725 5 (1991-03-01), None
patent: 0 319 273 5 (1991-08-01), None
patent: 0 404 964 9 (1992-02-01), None
patent: 0 434 189 6 (1992-11-01), None
patent: 0 531 552 6 (1993-11-01), None
patent: 0 605 326 4 (1994-02-01), None
patent: 0 603 723 9 (1994-02-01), None
patent: 0 608 994 7 (1994-03-01), None
patent: 0 613 245 3 (1994-05-01), None
patent: 0 820 394 5 (1996-08-01), None
patent: 0 827 423 4 (1996-10-01), None
Omi et al., “Development of 0.45-mm Thick Ultra-Thin Small Outline Package”, IEEE Trans. on Components, Packaging, and Manufacturing Tech., pp. 471-477, Aug. 1995.*
Ward, W. C., “Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Technique”, Proceedings of the 38th Electronics Components Conference, 1988., pp. 552-557, May 9-11, 1988.
Kawano Hiroshi
Ohuchi Shinji
Shiraishi Yasushi
Yamada Etsuo
Jones Volentine, P.L.L.C
Malsawma Lex H.
OKI Electric Industry Co., Ltd.
Smith Matthew
LandOfFree
Method of fabricating a semiconductor device having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a semiconductor device having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a semiconductor device having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2495778