Method of fabricating a semiconductor device

Details Method of fabricating a semiconductor device Method of fabricating a semiconductor device

2002-02-05

2003-06-17

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S689000, C438S694000, C438S695000, C438S696000, C438S700000, C438S706000, C438S710000, C438S711000, C438S719000, C438S789000, C438S790000

Reexamination Certificate

active

06579808

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating semiconductor devices, and more particularly, to a method of fabricating semiconductor devices capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined.
2. Description of the Related Art
As is generally known, contact holes are employed as connection paths for electrically connected semiconductor devices and act as wiring or upper and lower wiring. Conventionally, the wiring is formed by filling metal into the contact hole.
However, as semiconductor devices become highly integrated, the size of the contact hole necessarily must be decreased. Therefore, recent efforts are focused on decreasing the size of the contact hole.
FIGS. 1A
to
1
D are cross sectional views for showing the steps of a conventional method for fabricating semiconductor devices and
FIG. 2
is a TEM photograph of the structure shown in FIG.
1
C.
Referring to
FIG. 1A
, oxidized silicon is deposited on a semiconductor substrate
100
including a transistor in accordance with a Chemical Vapor Deposition (hereinafter, referred to as CVD) process, thereby forming an insulating layer
104
. Then, an Organic Bottom Anti-Reflective Coating layer
106
is formed on the insulating layer
104
. The Anti-Reflective Coating layer
106
prevents reflection of exposed light in the following exposure process.
In the drawings, identification numeral
102
indicates conductive regions, such as source/drain, and al illustrates the minimum size of the contact hole defined with recent photo devices, being approximately between 0.16 and 0.18 &mgr;m, and desirably, 0.17 &mgr;m.
Subsequently, photoresist is applied on the Anti-Reflective Coating layer
106
and exposure and development processes are performed to form a photoresist (PR) pattern
108
exposing a part corresponding to the conductive regions
102
. In order to minimize the size of the part exposing the part corresponding to the conductive regions on the photoresist pattern, the photoresist pattern is made by using a thermal flow process.
Referring to
FIG. 1B
, the Anti-Reflective Coating layer is removed by a first dry etch process
120
using the photoresist pattern PR
108
as a mask. The first dry etch process is performed by using a mixed gas comprising CH
4
, Ar and O
2
as an etching gas, wherein the Anti-Reflective Coating layer exposed by the photoresist pattern PR
108
is removed by chemical reaction with the mixed gas. The Anti-Reflective Coating layer
107
remains after the first dry etch process. The remaining Anti-Reflective Coating layer
107
has a vertical profile.
Referring to
FIGS. 1C and 2
, the insulating layer
104
is removed in accordance with a second dry etch process
122
using the photoresist pattern PR
108
as a mask, thereby forming a contact hole
130
. The second dry etch process
122
is performed by using a mixed gas comprising C
4
H
8
, CH
2
F
2
and Ar as etching gas. The insulating layer exposed by the photoresist pattern (PR)
108
is removed by chemical reaction with the mixed gas.
The contact hole
130
has a size the same as that of the contact hole originally to be defined, that is, between 0.16 and 0.18 &mgr;m, and desirably 0.17 &mgr;m.
The insulating layer
105
remains after the second dry etch process
122
.
Referring to
FIG. 1D
, the photoresist pattern (PR)
108
and the remaining Anti-Reflective Coating layer
107
are removed by a conventional process, such as polishing.
Referring to
FIG. 1E
, a metal layer is formed on the resulting structure by sputtering metal to cover the contact hole
130
and a pattern etch process is performed on the metal layer, thereby forming a bit line
132
, as shown.
The following table 1 shows wafer CD values according to the conventional method, wherein ‘C’ indicates the center of the wafer, ‘L’ left of the center C, ‘R’ right of the center C, ‘T’ top, ‘B’ bottom, ‘LT’ is at a 45° angle between the left L and the top T, ‘RT’ is at a 45° angle between the right R and the top T, ‘RB’ is at a 45° angle between the right R and the bottom B and ‘LB’ is at a 45° angle between the left L and the bottom B.
TABLE 1
CD value (&mgr;m)
layer
L
B
C
T
R
LT
RT
RB
LB
Mean
Insulating
0.145
0.1500
0.1550
0.1450
0.1440
0.1770
0.1800
0.1650
0.1680
0.1588
layer(105)
According to the conventional method, the contact hole having a dimension between 0.16 and 0.18 &mgr;m is obtained. However, it is difficult to fabricate a contact hole below 0.14 &mgr;m. A further problem is encountered in lowering the Critical Dimension CD uniformity of a wafer, since the reflow process is performed on the photoresist pattern.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above-mentioned problems and the object of the present invention is to provide a method of fabricating semiconductor devices capable of controlling the size of contact hole for bit line formation below 0.14 &mgr;m.
In order to accomplish the above object, the present invention comprises the steps of: forming an insulating layer and an Anti-Reflective Coating layer on a substrate, the substrate including conductive regions; forming a photoresist pattern opening over the conductive regions on the Anti-Reflective Coating layer; etching the Anti-Reflective Coating layer in accordance with a first dry etch process using a mixed gas of SO
2
and He and employing the photoresist pattern as an etch mask and at the same time, forming a polymer sidewall by attaching polymer generated in the first dry etch process to the sides of the remaining Anti-Reflective Coating layer; forming a contact hole by removing the insulating layer in accordance with a second dry etch process employing the photoresist pattern and the polymer sidewall as an etch mask; and removing the photoresist pattern, the remaining Anti-Reflective Coating layer and the polymer sidewall.


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