Method of fabricating a semiconductor device

Details Method of fabricating a semiconductor device Method of fabricating a semiconductor device

1999-10-19

2003-01-28

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including isolation structure

C438S301000, C438S306000

Reexamination Certificate

active

06511890

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention related to a method of fabricating a semiconductor device which prevents short channel hump due to the moisture in an insulating interlayer.
2. Discussion of Related Art
As semiconductor devices are highly integrated, techniques of reducing the device isolating area which is so-called field area occupying relatively large area in a semiconductor device have been developed so far.
In a general method of fabricating semiconductor devices, devices are isolated by local oxidation of silicon(hereinafter abbreviated LOCOS) which oxidizes a field area of a semiconductor substrate thermally. Bird's beaks are formed, when LOCOS is carried out, as oxygens are diffused to the horizontal direction along with a buffer oxide layer. Therefore, active layers are reduced in size to increase device sizes. That's why various methods of reducing bird's beak size as well as isolating devices have been developed.
Shallow trench isolation(hereinafter abbreviated STI), which forms a field oxide layer by forming a trench in a field area of a semiconductor substrate and by filling up the trench with insulating substance to isolated devices, is very useful for reducing a chip size and planarizing a surface of the substrate.
FIG. 1A
to
FIG. 1E
show a method of fabricating a semiconductor device according to a related art.
Referring to
FIG. 1A
, a buffer oxide
13
is formed on a p typed semiconductor substrate
11
by thermal oxidation. A mask layer
15
is formed by depositing silicon nitride on the buffer oxide layer
13
by chemical vapor deposition(hereinafter abbreviated CVD).
A device isolating area and an active area are defined by patterning the mask and buffer oxide layers
15
and
13
selectively to expose a surface of the semiconductor substrate
11
by photolithography. Then, trenches
17
are formed by etching the exposed surface of the semiconductor substrate
11
by anisotropic etch such as reactive ion etching(hereinafter abbreviated RIE) or plasma etch.
Referring to
FIG. 1
b,
silicon oxide is deposited on the mask layer
15
to fill up the trenches
17
by CVD. And, silicon oxide is etched back to expose the mask layer
15
only to remain inside the trenches
17
by chemical mechanical polishing(hereinafter abbreviated CMP) or RIE. In this case, the silicon oxide just remaining inside the trenches
17
becomes a field oxide layer
19
isolating devices.
An active area of the semiconductor substrate
11
is exposed by removing the mask and pad oxide layers
15
and
13
successively by wet etch. In this case, step difference is reduces as the portion of the field oxide layer
19
which is higher than the surface of the substrate
11
is etched away.
Referring to
FIG. 1C
, a gate
23
is formed by inserting a gate oxide layer
21
in the active area on the semiconductor substrate
11
. The gate oxide layer
21
is formed by oxidizing a surface of the semiconductor substrate
11
. The gate
23
is formed by depositing polysilicon doped with impurities on the gate oxide layer
21
by CVD then by patterning the polysilicon to expose the semiconductor substrate
11
by photolithography. In this case, the gate
23
is patterned to the direction of the width of a device, which is perpendicular to the length direction of the device as well as the cross section, overlapped with a predetermined portion of the field oxide layer
19
.
Lightly doped regions
25
used as an LDD(lightly doped drain) region are formed by implanting n typed impurities with low dose and energy into the semiconductor substrate
11
in use of the gate
23
as a mask.
Referring to
FIG. 1D
, insulator such as silicon oxide and the like is deposited on the semiconductor substrate
11
to cover the gate
23
by CVD. And, a sidewall spacer
27
is formed at the lateral sides of the gate
23
by etching back the insulator to expose the semiconductor substrate
11
.
Heavily doped regions
29
used for source and drain regions overlapped with the lightly doped regions
25
are formed by implanting n typed impurity ions into the semiconductor substrate
11
with heavy dose and energy in use of the gate
23
and sidewall spacer
27
as a mask. In this case, the portion of the semiconductor substrate
11
, which is free from being implanted with impurities, under the gate
23
becomes a channel region of a device.
Referring to
FIG. 1E
, an insulating interlayer
31
covering the gate
23
and sidewall spacer
27
is formed on the semiconductor substrate
11
. In this case, the insulating interlayer
31
is formed to improve the planarization of the surface by depositing TEOS(Tetraethyl orthosilicate) by LPCVD(Low Pressure CVD) or PECVD(Plasma Enhanced CVD).
An etch-stop layer
33
is formed by depositing silicon nitride on the insulating interlayer
31
by CVD. A contact hole
35
exposing the heavily doped region
29
is formed by patterning the etch-stop layer
33
and insulating interlayer
31
by photolithography.
In the contact hole
35
, a plug connecting a capacitor to the heavily doped region
29
will be formed. The etch-stop layer
33
prevents the insulating interlayer
31
from being etched when polysilicon is patterned to form capacitor electrodes.
As mentioned in the above explanation of the method of fabricating a semiconductor device, planarization of the surface is improved as the insulating interlayer is formed by depositing TEOS by PECVD or LPCVD.
Unfortunately, as LPCVD or PECVD for depositing TEOS is carried out at low temperature, moisture having less evaporating tendency remains inside when the insulating interlayer is formed. Therefore, the moisture fails to diffuse outside but diffuse downward when the etch-stop layer is formed and treated thermally. And, the moisture diffuses into the comers of the gate through the interface between the semiconductor substrate and field oxide, generating positive fixed charge. Thus, stand-by current is increased as breakdown voltage in the lightly doped regions to the direction of device width of an NMOS transistor is lowered.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a semiconductor device that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a method of fabricating a semiconductor device which prevents stand-by current from increasing due to the breakdown voltage drop in the lightly doped region to the direction of device width.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention.
The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming a trench typed field oxide layer defining an active area in a field area of a semiconductor substrate of a first conductive type, forming a gate to the direction of device width wherein a gate oxide layer is inserted between the gate and semiconductor substrate, forming impurity regions in the semiconductor substrate at both sides of the gate by ion implantation with impurities of a second conductive type, forming an insulating interlayer covering the gate on the semiconductor substrate, and removing moisture contained in the insulating interlayer by thermal treatment.
In another aspect, the present invention includes the steps of forming a trench defining an active area on the field area in a semiconductor substrate of a first conductive type, forming a field oxide layer in the trench, forming a gate oxide layer and an electrically-conductive layer, forming a gate long to the direction of device width on the fi

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