Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2000-06-21
2002-03-19
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S050000, C438S151000, C438S149000
Reexamination Certificate
active
06358766
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a semiconductor film having a crystal structure, on a substrate having an insulating surface, and also to a method of fabricating a semiconductor device which employs the semiconductor film as an active layer. More particularly, it relates to a method of fabricating a thin film transistor in which an active layer is formed of a crystalline semiconductor film. Incidentally, here in this specification, the expression “semiconductor device” is intended to signify general devices which can function by utilizing semiconductor properties, and it shall cover within its category, an electro-optical device which is represented by a liquid crystal display device of active matrix type formed using thin film transistors, and an electronic equipment in which such an electro-optical device is installed as a component.
2. Description of the Related Art
There have been developed thin film transistors (hereinbelow, often abbreviated to “TFTs”) each of which employs as its active layer a crystalline semiconductor film prepared in such a way that an amorphous semiconductor film is formed on an insulating substrate having a light transmissivity, such as of glass, and then crystallized by laser annealing, thermal annealing or the like. A glass substrate of barium borosilicate glass, alumino-borosilicate glass or the like is often employed as the insulating substrate. Although such a glass substrate is inferior to a quartz substrate in the point of a heat resistance, it is inexpensive on the market, and hence, it has the merit of being capable of the easy manufacture of a large area substrate.
The laser annealing is known as a crystallizing technique which can crystallize the amorphous semiconductor film by giving high energy on only this film without considerably raising the temperature of the glass substrate. In particular, an excimer laser which emits light of short wavelengths at a large power is considered most suited for this use. The laser annealing with the excimer laser is carried out in such a way that a laser beam is worked by an optical system so as to define a spot or a line on a surface to-be-irradiated, and that the surface to-be-irradiated is scanned by the worked laser beam (i. e., that the projected position of the laser beam is moved relatively to the surface to-be-irradiated). The excimer laser annealing with, for example, the rectilinear laser beam is also capable of laser-annealing the whole surface to-be-irradiated by the scanning in only a direction orthogonal to the longitudinal direction of the surface, and it is excellent in productivity. It is therefore becoming the mainstream as the manufacturing technology of a liquid crystal display device employing TFTs.
The laser annealing is applicable to the crystallization of various semiconductor materials. So far, however, a high field-effect mobility has been realized by employing a crystalline silicon film for the active layer of each TFT. The technology has incarnated a liquid crystal display device of monolithic type wherein pixel TFTs constituting pixel portions, and the TFTs of driver circuits to be disposed around the pixel portions are formed on a single glass substrate.
However, the crystalline silicon film prepared by the laser annealing has been formed in the shape of the aggregate of a plurality of crystal grains, and the locations and sizes of the crystal grains have been random. It has accordingly been impossible to form the crystalline silicon film with the locations and sizes of the crystal grains designated. The interfaces of the crystal grains (grain boundaries) have involved causes for degrading the current transport characteristics of carriers under the influences of recombination centers and trapping centers ascribable to amorphous structures, crystal defects etc., and potential levels at the grain boundaries. Nevertheless, it has been next to impossible that a channel forming region, in which the property of a crystal affects the characteristics of the TFT seriously, is formed of a single crystal grain with the influences of the grain boundaries excluded. Until today, therefore, the TFT which employs the crystalline silicon film as its active layer has not attained characteristics comparable to those of a MOS transistor which is fabricated on a single-crystal silicon substrate.
As a method for solving such a problem, it is considered an effective expedient to enlarge the crystal grains and to control the locations of the large crystal grains, thereby to eliminate the crystal grain boundaries from the channel forming region. By way of example, “Location Control of Large Grain Following Excimer-Laser Melting of Si Thin-Films”, R. Ishihara and A. Burtsev, Japanese Journal of Applied Physics, vol. 37, No. 3B, pp. 1071-1075, 1988, discloses a method which realizes the location control of crystals and the enlargement of grains by controlling the temperature distribution of a silicon film in three dimensions. According to the method, a film of high-fusing metal is formed on a glass substrate, the metal film is overlaid with a silicon oxide film which partially differs in thickness, and an amorphous silicon film is formed on the surface of the silicon oxide film. It is reported that crystal grain diameters can be enlarged to several &mgr;m by irradiating both the surfaces of the resulting substrate with excimer laser beams.
The Ishihara et al. method features that the thermal characteristics of the base material of the amorphous silicon film are locally changed to control a heat flow to the substrate and to afford a temperature gradient. To that end, however, the three-layer structure of the high-fusing metal layer/silicon oxide layer/semiconductor film is formed on the glass substrate. It is structurally possible to fabricate a TFT of top gate type by employing the semiconductor film as an active layer. Since, however, a parasitic capacitance is incurred by the silicon oxide film interposed between the semiconductor film and the high-fusing metal layer, the power dissipation of the TFT increases, and the high-speed operation thereof is difficult of attainment.
On the other hand, the three-layer structure is considered to be effectively applicable to a TFT of bottom gate type or inverse stagger type by employing the high-fusing metal layer as a gate electrode. In the three-layer structure, however, even when the thickness of the semiconductor film is excluded, the total thickness of the high-fusing metal layer and the silicon oxide layer is problematic. More specifically, since a thickness suitable for the crystallizing process does not always agree with a thickness suitable for the characteristics of the TFT element, both the optimum design of the structure for the crystallizing process and the optimum design thereof for the element characteristics cannot be satisfied simultaneously.
Besides, when the high-fusing metal layer having no light transmissivity is formed on the whole surface of the glass substrate, a liquid crystal display device of transmission type cannot be fabricated. The high-fusing metal layer is useful in the point of a high thermal conductivity. Since, however, a chromium (Cr) film or titanium (Ti) film used as the high-fusing metal material exhibits a high internal stress, a problem will occur as to the close adhesion of the metal film with the glass substrate at a high possibility. Further, the internal stress may possibly exert influence even on the semiconductor film overlying the metal film and act as a force distorting the crystalline semiconductor film formed.
Meanwhile, for the purpose of controlling into a predetermined range a threshold voltage (hereinbelow, denoted as “Vth”) which is an important characteristic parameter for the TFT, it has been required besides the control of the valence electrons of the channel forming region, to lower the charged defect densities of the base film and a gate insulating film which are respectively formed of insulating films in close touch with
Bowers Charles
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Schillinger Laura M.
Semiconductor Energy Laboratory Co,. Ltd.
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