Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-03-12
2004-11-02
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S612000, C365S158000
Reexamination Certificate
active
06812040
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor memory devices.
More particularly, the present invention relates to improved methods of fabricating semiconductor random access memory devices that utilize a magnetic field.
BACKGROUND OF THE INVENTION
A magnetoresistive random access memory (hereinafter referred to as “MRAM”) device has a structure which includes ferromagnetic layers separated by a non-ferromagnetic layer. Information is stored as directions of magnetization vectors in magnetic layers. Magnetic vectors in one magnetic layer, for instance, are magnetically fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite directions which are called “Parallel” and “Anti-parallel” states, respectively. In response to Parallel and Anti-parallel states, the magnetic memory element represents two different resistances. The resistance indicates minimum and maximum values when the magnetization vectors of two magnetic layers point in substantially the same and opposite directions, respectively. Accordingly, a detection of changes in resistance allows an MRAM device to provide information stored in the magnetic memory element.
A MRAM device integrates magnetic memory elements and other circuits, for example, a control circuit for magnetic memory elements, comparators, for detecting states in a magnetic memory element, input/output circuits, etc. These circuits are fabricated in the process of complimentary metal oxide semiconductor (hereinafter referred to as “CMOS”) technology in order to lower the power consumption of the MRAM device. The CMOS process requires high temperature steps which exceeds 300° C. for depositing dielectric and metal layers and annealing implants, for example.
Magnetic layers employ ferromagnetic materials such as nickel-iron, cobalt-iron, and nickel-iron-cobalt which require processing below 300° C. in order to prevent intermixing of magnetic materials caused by high temperatures. Accordingly, magnetic memory elements need to be fabricated at a different stage after CMOS processing.
Further, magnetic memory elements contain components that are easily oxidized and also sensitive to corrosion. To protect magnetic memory elements from degradation and keep the performance and reliability of the MRAM device, a passivation layer is formed over magnetic memory elements.
In addition, a magnetic memory element includes very thin layers, some of which are tens of angstroms thick. The performance of the magnetic memory element is sensitive to the surface conditions on which magnetic layers are deposited. Accordingly, it is necessary to make a flat surface to prevent the characteristics of a MRAM device from degrading. Also, magnetic memory elements are typically very small which makes it extremely difficult to connect the magnetic memory element to circuitry by using photolithography processes where the alignment tolerances are tight. Further, the materials comprising the ferromagnetic layers are difficult to etch because they are typically non-volatile in conventional low temperature plasmas and are very thin which makes them sensitive to corrosion from conventional chlorine based chemistries.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
SUMMARY OF THE INVENTION
To achieve the objects and advantages specified above and others, an improved method of fabricating a MRAM device with a self-aligned via is disclosed. The method involves forming magnetic memory elements on circuitry for controlling operations of magnetic memory elements. First, the circuitry is formed on a substrate under the CMOS process which requires a heat treatment of 300° C. or more. While fabricating the circuitry, conductive lines are also formed, which are used to create magnetic fields for writing and/or reading states in the magnetic memory element. The metal lines may or may not be enclosed by high permeability material such as a permalloy layer which facilitates magnetic fields to concentrate on the magnetic memory element. After completion of the circuitry, a surface of a layer including the circuitry is polished by the chemical mechanical polishing (hereinafter referred to as “CMP”) process which produces a flat surface on the layer including the circuitry, then the magnetic memory element has a metal cap formed thereon. The flat surface prevents the characteristics of the magnetic memory element from degrading. Fabrication of the magnetic memory element after the CMOS process improves the performance and reliability of the magnetic memory element and avoids thermal degradation of the magnetic memory element.
Further, the metal cap on the MRAM device is used as a seed layer to electrochemically deposit a bump metal layer. By using the metal cap as the seed layer, difficult and expensive photolithography processing steps typically used to form an electrically conductive via are avoided. A dielectric layer is deposited on the exposed surface and CMP or a similar process is used to expose the bump metal layer and form a flat surface wherein a bit line is formed adjacent to the bump metal layer.
REFERENCES:
patent: 6165803 (2000-12-01), Chen et al.
patent: 6180523 (2001-01-01), Lee et al.
patent: 6211090 (2001-04-01), Durlam et al.
patent: 6413788 (2002-07-01), Tuttle
patent: 6555858 (2003-04-01), Jones et al.
patent: 2002/0097600 (2002-07-01), Ning
patent: 1 085 586 (2001-03-01), None
patent: WO 02/19338 (2002-03-01), None
Wang et al., “Magnetostatic coupline in spin dependent tunnel junctions,” IEEE Transactions on Magnetics, vol. 36, No. 5, Sep. 5, 2000, pp. 2802-2805.
Butcher Brian
D'urso John J.
Durlam Mark A.
Grynkewich Gregory W.
Kyler Kelly
Chaudhari Chandra
Freescale Semiconductor Inc.
Ingrassia Fisher & Lorenz PC
Pham Thanhha
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