Fishing – trapping – and vermin destroying
Patent
1988-09-23
1990-05-08
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 39, 437189, 437200, 437912, 437177, H01L 2128
Patent
active
049238230
ABSTRACT:
A method of producing a semiconductor device, such as a MESFET having a self-aligned gate. A triple layer film is formed on the semiconductor substrate. The lowermost layer is a high melting point metal silicide, the intermediate layer a thin high melting point metal and the upper layer an insulator. The thicknesses and etching rates of the layers are selected such that the thin intermediate metal layer protects the underlying silicide and overlying insulator layers during etching. The three layers are anisotropically etched to produce a well-formed gate structure which is used as a mask in an ion implantation step for forming source and drain regions. A subsequent selective etching process removes the insulator layer (which serves as a dummy gate) exposing the underlying silicide layer on which is deposited a low resistance metal such as gold in a self-aligned fashion thereby to improve the high frequency performance of the device.
REFERENCES:
patent: 4285761 (1981-08-01), Fatula Jr. et al.
patent: 4322453 (1982-03-01), Miller
patent: 4574298 (1986-03-01), Yamagishi et al.
patent: 4700455 (1087-10-01), Shimada et al.
Hearn Brian E.
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tuan
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