Method of fabricating a self-aligned metal-semiconductor FET hav

Details Method of fabricating a self-aligned metal-semiconductor FET hav Method of fabricating a self-aligned metal-semiconductor FET hav

1986-06-18

1987-12-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437234, 437176, 156656, 357 232, H01L 21302

Patent

active

047118580

ABSTRACT:
A method for the fabrication of self-aligned MESFET structures with a recessed refractory submicron gate. After channel formation on a semi-insulating (SI) substrate, which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing, refractory gate material is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of, e.g., GaAs, using MOCVD of MBE processes resulting in poly-crystalline material over the gate "mask" and mono-crystalline material on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes. In order to further improve process reliability, insulating sidewalls are provided at the vertical edges of the gate to avoid source-gate and drain-gate shorts.

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